mem64.isa (14058:a17b827fbf5e) mem64.isa (14150:1391e94a7b95)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 715 unchanged lines hidden (view full) ---

724 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
725 (IntRegIndex)_dest, _imm)
726 {
727 %(constructor)s;
728 assert(!%(use_uops)d);
729 setExcAcRel(exclusive, acrel);
730 }
731}};
1// -*- mode:c++ -*-
2
3// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 715 unchanged lines hidden (view full) ---

724 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
725 (IntRegIndex)_dest, _imm)
726 {
727 %(constructor)s;
728 assert(!%(use_uops)d);
729 setExcAcRel(exclusive, acrel);
730 }
731}};
732
733// Atomic operations in memory
734
735def template AmoOpExecute {{
736 Fault %(class_name)s::execute(ExecContext *xc,
737 Trace::InstRecord *traceData) const
738 {
739 Addr EA;
740 Fault fault = NoFault;
741
742 %(op_decl)s;
743 %(op_rd)s;
744 %(ea_code)s;
745
746 %(usrDecl)s;
747 if (fault == NoFault) {
748 %(memacc_code)s;
749 }
750
751 %(amo_code)s
752 assert(amo_op);
753
754 if (fault == NoFault) {
755 fault = amoMemAtomic(xc, traceData, Mem, EA,
756 memAccessFlags, amo_op);
757 }
758
759 if (fault == NoFault) {
760 %(postacc_code)s;
761 }
762
763 if (fault == NoFault) {
764 %(op_wb)s;
765 }
766
767 return fault;
768 }
769}};
770
771def template AmoOpInitiateAcc {{
772 Fault %(class_name)s::initiateAcc(ExecContext *xc,
773 Trace::InstRecord *traceData) const
774 {
775 Addr EA;
776 Fault fault = NoFault;
777
778 %(op_src_decl)s;
779 %(op_rd)s;
780 %(ea_code)s;
781 %(usrDecl)s;
782
783 if (fault == NoFault) {
784 %(memacc_code)s;
785 }
786
787 %(amo_code)s;
788
789 assert(amo_op);
790 if (fault == NoFault) {
791 fault = initiateMemAMO(xc, traceData, EA, Mem, memAccessFlags,
792 amo_op);
793 }
794
795 return fault;
796 }
797}};
798
799def template AmoOpCompleteAcc {{
800 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
801 Trace::InstRecord *traceData) const
802 {
803 Fault fault = NoFault;
804
805 %(op_decl)s;
806 %(op_rd)s;
807
808 // ARM instructions will not have a pkt if the predicate is false
809 getMem(pkt, Mem, traceData);
810
811 if (fault == NoFault) {
812 %(postacc_code)s;
813 }
814
815 if (fault == NoFault) {
816 %(op_wb)s;
817 }
818
819 return fault;
820 }
821
822}};
823
824def template AmoOpDeclare {{
825 class %(class_name)s : public %(base_class)s
826 {
827 public:
828
829 /// Constructor.
830 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
831 IntRegIndex _base, IntRegIndex _result);
832
833 Fault execute(ExecContext *, Trace::InstRecord *) const override;
834 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
835 Fault completeAcc(PacketPtr, ExecContext *,
836 Trace::InstRecord *) const override;
837
838 void
839 annotateFault(ArmFault *fault) override
840 {
841 %(fa_code)s
842 }
843 };
844}};
845
846
847def template AmoOpConstructor {{
848 %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 _dest, _base, _result)
852 {
853 %(constructor)s;
854
855 }
856}};
857
858def template AmoPairOpDeclare {{
859 class %(class_name)s : public %(base_class)s
860 {
861 public:
862 uint32_t d2_src ;
863 uint32_t r2_src ;
864 uint32_t r2_dst ;
865 /// Constructor.
866 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
867 IntRegIndex _base, IntRegIndex _result);
868
869 Fault execute(ExecContext *, Trace::InstRecord *) const override;
870 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
871 Fault completeAcc(PacketPtr, ExecContext *,
872 Trace::InstRecord *) const override;
873
874 void
875 annotateFault(ArmFault *fault) override
876 {
877 %(fa_code)s
878 }
879 };
880}};
881
882
883def template AmoPairOpConstructor {{
884 %(class_name)s::%(class_name)s(ExtMachInst machInst,
885 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
886 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
887 _dest, _base, _result)
888 {
889 %(constructor)s;
890
891 uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ;
892 uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
893
894 d2_src = _numSrcRegs ;
895 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, d2);
896 r2_src = _numSrcRegs ;
897 _srcRegIdx[_numSrcRegs++] = RegId(IntRegClass, r2);
898 r2_dst = _numDestRegs ;
899 _destRegIdx[_numDestRegs++] = RegId(IntRegClass, r2);
900
901 }
902}};
903
904def template AmoArithmeticOpDeclare {{
905 class %(class_name)s : public %(base_class)s
906 {
907 public:
908 bool isXZR ;
909 /// Constructor.
910 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
911 IntRegIndex _base, IntRegIndex _result);
912
913 Fault execute(ExecContext *, Trace::InstRecord *) const override;
914 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
915 Fault completeAcc(PacketPtr, ExecContext *,
916 Trace::InstRecord *) const override;
917
918 void
919 annotateFault(ArmFault *fault) override
920 {
921 %(fa_code)s
922 }
923 };
924}};
925
926def template AmoArithmeticOpConstructor {{
927 %(class_name)s::%(class_name)s(ExtMachInst machInst,
928 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
929 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
930 _dest, _base, _result)
931 {
932 %(constructor)s;
933 isXZR = false;
934 uint32_t r2 = RegId(IntRegClass, dest).index() ;
935 if (r2 == 31){
936 flags[IsReadBarrier] = false;
937 isXZR = true;
938 }
939 }
940}};