3c3
< // Copyright (c) 2011-2014 ARM Limited
---
> // Copyright (c) 2011-2014, 2017 ARM Limited
259c259,260
< %(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm);
---
> %(class_name)s(ExtMachInst machInst, IntRegIndex _base,
> MiscRegIndex _dest, uint64_t _imm);
273c274,275
< %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm)
---
> %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _base,
> MiscRegIndex _dest, uint64_t _imm)
275c277
< (IntRegIndex)_base, _dest, _imm)
---
> _base, _dest, _imm)