mem.isa (9250:dab0f29394f0) mem.isa (9573:cac6e95e236c)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1117 conditional = true;
1118 for (int x = 0; x < _numDestRegs; x++) {
1119 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1120 }
1121 }
1122#if %(use_uops)d
1123 assert(numMicroops >= 2);
1124 uops = new StaticInstPtr[numMicroops];
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 1108 unchanged lines hidden (view full) ---

1117 conditional = true;
1118 for (int x = 0; x < _numDestRegs; x++) {
1119 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1120 }
1121 }
1122#if %(use_uops)d
1123 assert(numMicroops >= 2);
1124 uops = new StaticInstPtr[numMicroops];
1125 if (_dest == INTREG_PC) {
1125 if (_dest == INTREG_PC && !isFloating()) {
1126 IntRegIndex wbIndexReg = index;
1127 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1128 _shiftAmt, _shiftType, _index);
1129 uops[0]->setDelayedCommit();
1130 uops[1] = new %(wb_decl)s;
1131 uops[1]->setDelayedCommit();
1132 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1133 uops[2]->setFlag(StaticInst::IsControl);

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1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1152 _shiftAmt, _shiftType, _index);
1153 uops[0]->setDelayedCommit();
1154 uops[1] = new %(wb_decl)s;
1155 uops[1]->setLastMicroop();
1156
1157 }
1158#else
1126 IntRegIndex wbIndexReg = index;
1127 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1128 _shiftAmt, _shiftType, _index);
1129 uops[0]->setDelayedCommit();
1130 uops[1] = new %(wb_decl)s;
1131 uops[1]->setDelayedCommit();
1132 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1133 uops[2]->setFlag(StaticInst::IsControl);

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1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1152 _shiftAmt, _shiftType, _index);
1153 uops[0]->setDelayedCommit();
1154 uops[1] = new %(wb_decl)s;
1155 uops[1]->setLastMicroop();
1156
1157 }
1158#else
1159 if (_dest == INTREG_PC) {
1159 if (_dest == INTREG_PC && !isFloating()) {
1160 flags[IsControl] = true;
1161 flags[IsIndirectControl] = true;
1162 if (conditional)
1163 flags[IsCondControl] = true;
1164 else
1165 flags[IsUncondControl] = true;
1166 }
1167#endif

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1180 conditional = true;
1181 for (int x = 0; x < _numDestRegs; x++) {
1182 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1183 }
1184 }
1185#if %(use_uops)d
1186 assert(numMicroops >= 2);
1187 uops = new StaticInstPtr[numMicroops];
1160 flags[IsControl] = true;
1161 flags[IsIndirectControl] = true;
1162 if (conditional)
1163 flags[IsCondControl] = true;
1164 else
1165 flags[IsUncondControl] = true;
1166 }
1167#endif

--- 12 unchanged lines hidden (view full) ---

1180 conditional = true;
1181 for (int x = 0; x < _numDestRegs; x++) {
1182 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1183 }
1184 }
1185#if %(use_uops)d
1186 assert(numMicroops >= 2);
1187 uops = new StaticInstPtr[numMicroops];
1188 if (_dest == INTREG_PC) {
1188 if (_dest == INTREG_PC && !isFloating()) {
1189 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1190 _imm);
1191 uops[0]->setDelayedCommit();
1192 uops[1] = new %(wb_decl)s;
1193 uops[1]->setDelayedCommit();
1194 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1195 uops[2]->setFlag(StaticInst::IsControl);
1196 uops[2]->setFlag(StaticInst::IsIndirectControl);

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1203 uops[2]->setLastMicroop();
1204 } else {
1205 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1206 uops[0]->setDelayedCommit();
1207 uops[1] = new %(wb_decl)s;
1208 uops[1]->setLastMicroop();
1209 }
1210#else
1189 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1190 _imm);
1191 uops[0]->setDelayedCommit();
1192 uops[1] = new %(wb_decl)s;
1193 uops[1]->setDelayedCommit();
1194 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1195 uops[2]->setFlag(StaticInst::IsControl);
1196 uops[2]->setFlag(StaticInst::IsIndirectControl);

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1203 uops[2]->setLastMicroop();
1204 } else {
1205 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1206 uops[0]->setDelayedCommit();
1207 uops[1] = new %(wb_decl)s;
1208 uops[1]->setLastMicroop();
1209 }
1210#else
1211 if (_dest == INTREG_PC) {
1211 if (_dest == INTREG_PC && !isFloating()) {
1212 flags[IsControl] = true;
1213 flags[IsIndirectControl] = true;
1214 if (conditional)
1215 flags[IsCondControl] = true;
1216 else
1217 flags[IsUncondControl] = true;
1218 }
1219#endif
1220 }
1221}};
1222
1212 flags[IsControl] = true;
1213 flags[IsIndirectControl] = true;
1214 if (conditional)
1215 flags[IsCondControl] = true;
1216 else
1217 flags[IsUncondControl] = true;
1218 }
1219#endif
1220 }
1221}};
1222