mem.isa (8607:5fb918115c07) mem.isa (9250:dab0f29394f0)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1150 IntRegIndex wbIndexReg = index;
1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1152 _shiftAmt, _shiftType, _index);
1153 uops[0]->setDelayedCommit();
1154 uops[1] = new %(wb_decl)s;
1155 uops[1]->setLastMicroop();
1156
1157 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 1141 unchanged lines hidden (view full) ---

1150 IntRegIndex wbIndexReg = index;
1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1152 _shiftAmt, _shiftType, _index);
1153 uops[0]->setDelayedCommit();
1154 uops[1] = new %(wb_decl)s;
1155 uops[1]->setLastMicroop();
1156
1157 }
1158#else
1159 if (_dest == INTREG_PC) {
1160 flags[IsControl] = true;
1161 flags[IsIndirectControl] = true;
1162 if (conditional)
1163 flags[IsCondControl] = true;
1164 else
1165 flags[IsUncondControl] = true;
1166 }
1158#endif
1159 }
1160}};
1161
1162def template LoadImmConstructor {{
1163 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1164 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,

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1193 uops[2]->setFlag(StaticInst::IsReturn);
1194 uops[2]->setLastMicroop();
1195 } else {
1196 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1197 uops[0]->setDelayedCommit();
1198 uops[1] = new %(wb_decl)s;
1199 uops[1]->setLastMicroop();
1200 }
1167#endif
1168 }
1169}};
1170
1171def template LoadImmConstructor {{
1172 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1173 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1174 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,

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1202 uops[2]->setFlag(StaticInst::IsReturn);
1203 uops[2]->setLastMicroop();
1204 } else {
1205 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1206 uops[0]->setDelayedCommit();
1207 uops[1] = new %(wb_decl)s;
1208 uops[1]->setLastMicroop();
1209 }
1210#else
1211 if (_dest == INTREG_PC) {
1212 flags[IsControl] = true;
1213 flags[IsIndirectControl] = true;
1214 if (conditional)
1215 flags[IsCondControl] = true;
1216 else
1217 flags[IsUncondControl] = true;
1218 }
1201#endif
1202 }
1203}};
1204
1219#endif
1220 }
1221}};
1222