mem.isa (8207:cad97f04eb91) mem.isa (8442:b1f3dfae06f1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 73 unchanged lines hidden (view full) ---

82 %(op_rd)s;
83 %(ea_code)s;
84
85 if (%(predicate_test)s)
86 {
87 %(preacc_code)s;
88
89 if (fault == NoFault) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 73 unchanged lines hidden (view full) ---

82 %(op_rd)s;
83 %(ea_code)s;
84
85 if (%(predicate_test)s)
86 {
87 %(preacc_code)s;
88
89 if (fault == NoFault) {
90 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
91 EA, memAccessFlags, &memData);
90 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
91 &memData);
92 }
93
94 if (fault == NoFault) {
95 %(postacc_code)s;
96 }
97
98 if (fault == NoFault) {
99 %(op_wb)s;

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118 %(op_rd)s;
119 %(ea_code)s;
120
121 if (%(predicate_test)s)
122 {
123 %(preacc_code)s;
124
125 if (fault == NoFault) {
92 }
93
94 if (fault == NoFault) {
95 %(postacc_code)s;
96 }
97
98 if (fault == NoFault) {
99 %(op_wb)s;

--- 18 unchanged lines hidden (view full) ---

118 %(op_rd)s;
119 %(ea_code)s;
120
121 if (%(predicate_test)s)
122 {
123 %(preacc_code)s;
124
125 if (fault == NoFault) {
126 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
127 memAccessFlags, &memData);
126 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
127 &memData);
128 }
129 } else {
130 xc->setPredicate(false);
131 }
132
133 return fault;
134 }
135}};

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142 Fault fault = NoFault;
143
144 %(op_decl)s;
145 %(op_rd)s;
146
147 if (%(predicate_test)s)
148 {
149 // ARM instructions will not have a pkt if the predicate is false
128 }
129 } else {
130 xc->setPredicate(false);
131 }
132
133 return fault;
134 }
135}};

--- 6 unchanged lines hidden (view full) ---

142 Fault fault = NoFault;
143
144 %(op_decl)s;
145 %(op_rd)s;
146
147 if (%(predicate_test)s)
148 {
149 // ARM instructions will not have a pkt if the predicate is false
150 uint64_t memData = pkt->get<typeof(Mem)>();
150 getMem(pkt, Mem, traceData);
151 uint64_t memData = Mem;
151
152 %(postacc_code)s;
153
154 if (fault == NoFault) {
155 %(op_wb)s;
156 }
157 }
158

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169
170 %(op_decl)s;
171 %(op_rd)s;
172 %(ea_code)s;
173
174 if (%(predicate_test)s)
175 {
176 if (fault == NoFault) {
152
153 %(postacc_code)s;
154
155 if (fault == NoFault) {
156 %(op_wb)s;
157 }
158 }
159

--- 10 unchanged lines hidden (view full) ---

170
171 %(op_decl)s;
172 %(op_rd)s;
173 %(ea_code)s;
174
175 if (%(predicate_test)s)
176 {
177 if (fault == NoFault) {
177 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
178 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
178 %(memacc_code)s;
179 }
180
181 if (fault == NoFault) {
182 %(op_wb)s;
183 }
184 } else {
185 xc->setPredicate(false);

--- 50 unchanged lines hidden (view full) ---

236
237 if (%(predicate_test)s)
238 {
239 if (fault == NoFault) {
240 %(memacc_code)s;
241 }
242
243 if (fault == NoFault) {
179 %(memacc_code)s;
180 }
181
182 if (fault == NoFault) {
183 %(op_wb)s;
184 }
185 } else {
186 xc->setPredicate(false);

--- 50 unchanged lines hidden (view full) ---

237
238 if (%(predicate_test)s)
239 {
240 if (fault == NoFault) {
241 %(memacc_code)s;
242 }
243
244 if (fault == NoFault) {
244 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
245 memAccessFlags, NULL);
245 fault = writeMemAtomic(xc, traceData, Mem, EA,
246 memAccessFlags, NULL);
246 }
247
248 if (fault == NoFault) {
249 %(op_wb)s;
250 }
251 } else {
252 xc->setPredicate(false);
253 }

--- 55 unchanged lines hidden (view full) ---

309 {
310 if (fault == NoFault) {
311 %(memacc_code)s;
312 }
313
314 uint64_t writeResult;
315
316 if (fault == NoFault) {
247 }
248
249 if (fault == NoFault) {
250 %(op_wb)s;
251 }
252 } else {
253 xc->setPredicate(false);
254 }

--- 55 unchanged lines hidden (view full) ---

310 {
311 if (fault == NoFault) {
312 %(memacc_code)s;
313 }
314
315 uint64_t writeResult;
316
317 if (fault == NoFault) {
317 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
318 memAccessFlags, &writeResult);
318 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
319 &writeResult);
319 }
320
321 if (fault == NoFault) {
322 %(postacc_code)s;
323 }
324
325 if (fault == NoFault) {
326 %(op_wb)s;

--- 19 unchanged lines hidden (view full) ---

346
347 if (%(predicate_test)s)
348 {
349 if (fault == NoFault) {
350 %(memacc_code)s;
351 }
352
353 if (fault == NoFault) {
320 }
321
322 if (fault == NoFault) {
323 %(postacc_code)s;
324 }
325
326 if (fault == NoFault) {
327 %(op_wb)s;

--- 19 unchanged lines hidden (view full) ---

347
348 if (%(predicate_test)s)
349 {
350 if (fault == NoFault) {
351 %(memacc_code)s;
352 }
353
354 if (fault == NoFault) {
354 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
355 memAccessFlags, NULL);
355 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
356 NULL);
356 }
357 } else {
358 xc->setPredicate(false);
359 }
360
361 return fault;
362 }
363}};

--- 11 unchanged lines hidden (view full) ---

375
376 if (%(predicate_test)s)
377 {
378 if (fault == NoFault) {
379 %(memacc_code)s;
380 }
381
382 if (fault == NoFault) {
357 }
358 } else {
359 xc->setPredicate(false);
360 }
361
362 return fault;
363 }
364}};

--- 11 unchanged lines hidden (view full) ---

376
377 if (%(predicate_test)s)
378 {
379 if (fault == NoFault) {
380 %(memacc_code)s;
381 }
382
383 if (fault == NoFault) {
383 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
384 memAccessFlags, NULL);
384 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
385 NULL);
385 }
386 } else {
387 xc->setPredicate(false);
388 }
389
390 return fault;
391 }
392}};

--- 39 unchanged lines hidden (view full) ---

432
433 %(op_src_decl)s;
434 %(op_rd)s;
435 %(ea_code)s;
436
437 if (%(predicate_test)s)
438 {
439 if (fault == NoFault) {
386 }
387 } else {
388 xc->setPredicate(false);
389 }
390
391 return fault;
392 }
393}};

--- 39 unchanged lines hidden (view full) ---

433
434 %(op_src_decl)s;
435 %(op_rd)s;
436 %(ea_code)s;
437
438 if (%(predicate_test)s)
439 {
440 if (fault == NoFault) {
440 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
441 fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
441 }
442 } else {
443 xc->setPredicate(false);
444 }
445
446 return fault;
447 }
448}};

--- 35 unchanged lines hidden (view full) ---

484 Fault fault = NoFault;
485
486 %(op_decl)s;
487 %(op_rd)s;
488
489 if (%(predicate_test)s)
490 {
491 // ARM instructions will not have a pkt if the predicate is false
442 }
443 } else {
444 xc->setPredicate(false);
445 }
446
447 return fault;
448 }
449}};

--- 35 unchanged lines hidden (view full) ---

485 Fault fault = NoFault;
486
487 %(op_decl)s;
488 %(op_rd)s;
489
490 if (%(predicate_test)s)
491 {
492 // ARM instructions will not have a pkt if the predicate is false
492 Mem = pkt->get<typeof(Mem)>();
493 getMem(pkt, Mem, traceData);
493
494 if (fault == NoFault) {
495 %(memacc_code)s;
496 }
497
498 if (fault == NoFault) {
499 %(op_wb)s;
500 }

--- 703 unchanged lines hidden --- 		494
495 if (fault == NoFault) {
496 %(memacc_code)s;
497 }
498
499 if (fault == NoFault) {
500 %(op_wb)s;
501 }

--- 703 unchanged lines hidden ---