mem.isa (8140:7449084b1612) mem.isa (8203:78b9f056d58a)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1183 uint32_t _dest, uint32_t _base, bool _add,
1184 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1185 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1186 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1187 _shiftAmt, (ArmShiftType)_shiftType,
1188 (IntRegIndex)_index)
1189 {
1190 %(constructor)s;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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1183 uint32_t _dest, uint32_t _base, bool _add,
1184 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1185 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1186 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1187 _shiftAmt, (ArmShiftType)_shiftType,
1188 (IntRegIndex)_index)
1189 {
1190 %(constructor)s;
1191 bool conditional = false;
1191 if (!(condCode == COND_AL || condCode == COND_UC)) {
1192 if (!(condCode == COND_AL || condCode == COND_UC)) {
1193 conditional = true;
1192 for (int x = 0; x < _numDestRegs; x++) {
1193 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1194 }
1195 }
1196#if %(use_uops)d
1197 assert(numMicroops >= 2);
1198 uops = new StaticInstPtr[numMicroops];
1199 if (_dest == INTREG_PC) {
1200 IntRegIndex wbIndexReg = index;
1201 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1202 _shiftAmt, _shiftType, _index);
1203 uops[0]->setDelayedCommit();
1204 uops[1] = new %(wb_decl)s;
1205 uops[1]->setDelayedCommit();
1206 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1194 for (int x = 0; x < _numDestRegs; x++) {
1195 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1196 }
1197 }
1198#if %(use_uops)d
1199 assert(numMicroops >= 2);
1200 uops = new StaticInstPtr[numMicroops];
1201 if (_dest == INTREG_PC) {
1202 IntRegIndex wbIndexReg = index;
1203 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1204 _shiftAmt, _shiftType, _index);
1205 uops[0]->setDelayedCommit();
1206 uops[1] = new %(wb_decl)s;
1207 uops[1]->setDelayedCommit();
1208 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1209 uops[2]->setFlag(StaticInst::IsControl);
1210 uops[2]->setFlag(StaticInst::IsIndirectControl);
1211 if (conditional)
1212 uops[2]->setFlag(StaticInst::IsCondControl);
1213 else
1214 uops[2]->setFlag(StaticInst::IsUncondControl);
1207 uops[2]->setLastMicroop();
1208 } else if(_dest == _index) {
1209 IntRegIndex wbIndexReg = INTREG_UREG0;
1210 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1211 uops[0]->setDelayedCommit();
1212 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1213 _shiftAmt, _shiftType, _index);
1214 uops[1]->setDelayedCommit();

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1229
1230def template LoadImmConstructor {{
1231 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1232 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1233 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1234 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1235 {
1236 %(constructor)s;
1215 uops[2]->setLastMicroop();
1216 } else if(_dest == _index) {
1217 IntRegIndex wbIndexReg = INTREG_UREG0;
1218 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1219 uops[0]->setDelayedCommit();
1220 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1221 _shiftAmt, _shiftType, _index);
1222 uops[1]->setDelayedCommit();

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1237
1238def template LoadImmConstructor {{
1239 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1240 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1241 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1242 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1243 {
1244 %(constructor)s;
1245 bool conditional = false;
1237 if (!(condCode == COND_AL || condCode == COND_UC)) {
1246 if (!(condCode == COND_AL || condCode == COND_UC)) {
1247 conditional = true;
1238 for (int x = 0; x < _numDestRegs; x++) {
1239 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1240 }
1241 }
1242#if %(use_uops)d
1243 assert(numMicroops >= 2);
1244 uops = new StaticInstPtr[numMicroops];
1245 if (_dest == INTREG_PC) {
1246 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1247 _imm);
1248 uops[0]->setDelayedCommit();
1249 uops[1] = new %(wb_decl)s;
1250 uops[1]->setDelayedCommit();
1251 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1248 for (int x = 0; x < _numDestRegs; x++) {
1249 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1250 }
1251 }
1252#if %(use_uops)d
1253 assert(numMicroops >= 2);
1254 uops = new StaticInstPtr[numMicroops];
1255 if (_dest == INTREG_PC) {
1256 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1257 _imm);
1258 uops[0]->setDelayedCommit();
1259 uops[1] = new %(wb_decl)s;
1260 uops[1]->setDelayedCommit();
1261 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1262 uops[2]->setFlag(StaticInst::IsControl);
1263 uops[2]->setFlag(StaticInst::IsIndirectControl);
1264 if (conditional)
1265 uops[2]->setFlag(StaticInst::IsCondControl);
1266 else
1267 uops[2]->setFlag(StaticInst::IsUncondControl);
1268 if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
1269 uops[2]->setFlag(StaticInst::IsReturn);
1252 uops[2]->setLastMicroop();
1253 } else {
1254 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1255 uops[0]->setDelayedCommit();
1256 uops[1] = new %(wb_decl)s;
1257 uops[1]->setLastMicroop();
1258 }
1259#endif
1260 }
1261}};
1262
1270 uops[2]->setLastMicroop();
1271 } else {
1272 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1273 uops[0]->setDelayedCommit();
1274 uops[1] = new %(wb_decl)s;
1275 uops[1]->setLastMicroop();
1276 }
1277#endif
1278 }
1279}};
1280