mem.isa (8072:128afe2b3a35) mem.isa (8140:7449084b1612)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 903 unchanged lines hidden (view full) ---

912}};
913
914def template CompleteAccDeclare {{
915 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
916}};
917
918def template RfeConstructor {{
919 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 903 unchanged lines hidden (view full) ---

912}};
913
914def template CompleteAccDeclare {{
915 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
916}};
917
918def template RfeConstructor {{
919 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
920 uint32_t _base, int _mode, bool _wb)
921 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
922 (IntRegIndex)_base, (AddrMode)_mode, _wb)
920 uint32_t _base, int _mode, bool _wb)
921 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
922 (IntRegIndex)_base, (AddrMode)_mode, _wb)
923 {
924 %(constructor)s;
925 if (!(condCode == COND_AL || condCode == COND_UC)) {
926 for (int x = 0; x < _numDestRegs; x++) {
927 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
928 }
929 }
930#if %(use_uops)d
923 {
924 %(constructor)s;
925 if (!(condCode == COND_AL || condCode == COND_UC)) {
926 for (int x = 0; x < _numDestRegs; x++) {
927 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
928 }
929 }
930#if %(use_uops)d
931 assert(numMicroops >= 2);
932 uops = new StaticInstPtr[numMicroops];
933 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
934 uops[0]->setDelayedCommit();
935 uops[1] = new %(wb_decl)s;
936 uops[1]->setLastMicroop();
931 uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
932 int uopIdx = 0;
933 uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
934 uops[uopIdx]->setDelayedCommit();
935#if %(use_wb)d
936 uops[++uopIdx] = new %(wb_decl)s;
937 uops[uopIdx]->setDelayedCommit();
937#endif
938#endif
939#if %(use_pc)d
940 uops[++uopIdx] = new %(pc_decl)s;
941#endif
942 uops[uopIdx]->setLastMicroop();
943#endif
938 }
939}};
940
941def template SrsConstructor {{
942 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
943 uint32_t _regMode, int _mode, bool _wb)
944 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
945 (OperatingMode)_regMode, (AddrMode)_mode, _wb)

--- 311 unchanged lines hidden --- 		944 }
945}};
946
947def template SrsConstructor {{
948 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
949 uint32_t _regMode, int _mode, bool _wb)
950 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
951 (OperatingMode)_regMode, (AddrMode)_mode, _wb)

--- 311 unchanged lines hidden ---