mem.isa (7848:cc5e64f8423f) mem.isa (8072:128afe2b3a35)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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229 if (fault == NoFault) {
230 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
231 %(memacc_code)s;
232 }
233
234 if (fault == NoFault) {
235 %(op_wb)s;
236 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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229 if (fault == NoFault) {
230 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
231 %(memacc_code)s;
232 }
233
234 if (fault == NoFault) {
235 %(op_wb)s;
236 }
237 } else {
238 xc->setPredicate(false);
237 }
238
239 if (fault == NoFault && machInst.itstateMask != 0 &&
240 (!isMicroop() || isLastMicroop())) {
241 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
242 }
243
244 return fault;

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308 if (fault == NoFault) {
309 fault = xc->writeBytes(dataPtr, %(size)d, EA,
310 memAccessFlags, NULL);
311 }
312
313 if (fault == NoFault) {
314 %(op_wb)s;
315 }
239 }
240
241 if (fault == NoFault && machInst.itstateMask != 0 &&
242 (!isMicroop() || isLastMicroop())) {
243 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
244 }
245
246 return fault;

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310 if (fault == NoFault) {
311 fault = xc->writeBytes(dataPtr, %(size)d, EA,
312 memAccessFlags, NULL);
313 }
314
315 if (fault == NoFault) {
316 %(op_wb)s;
317 }
318 } else {
319 xc->setPredicate(false);
316 }
317
318 if (fault == NoFault && machInst.itstateMask != 0 &&
319 (!isMicroop() || isLastMicroop())) {
320 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
321 }
322
323 return fault;

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454 if (fault == NoFault) {
455 %(memacc_code)s;
456 }
457
458 if (fault == NoFault) {
459 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
460 memAccessFlags, NULL);
461 }
320 }
321
322 if (fault == NoFault && machInst.itstateMask != 0 &&
323 (!isMicroop() || isLastMicroop())) {
324 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
325 }
326
327 return fault;

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458 if (fault == NoFault) {
459 %(memacc_code)s;
460 }
461
462 if (fault == NoFault) {
463 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
464 memAccessFlags, NULL);
465 }
466 } else {
467 xc->setPredicate(false);
462 }
463
464 if (fault == NoFault && machInst.itstateMask != 0 &&
465 (!isMicroop() || isLastMicroop())) {
466 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
467 }
468
469 return fault;

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510 %(op_rd)s;
511 %(ea_code)s;
512
513 if (%(predicate_test)s)
514 {
515 if (fault == NoFault) {
516 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
517 }
468 }
469
470 if (fault == NoFault && machInst.itstateMask != 0 &&
471 (!isMicroop() || isLastMicroop())) {
472 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
473 }
474
475 return fault;

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516 %(op_rd)s;
517 %(ea_code)s;
518
519 if (%(predicate_test)s)
520 {
521 if (fault == NoFault) {
522 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
523 }
518 } else if (fault == NoFault && machInst.itstateMask != 0 &&
519 (!isMicroop() || isLastMicroop())) {
520 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
524 } else {
525 xc->setPredicate(false);
526 if (fault == NoFault && machInst.itstateMask != 0 &&
527 (!isMicroop() || isLastMicroop())) {
528 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
529 }
521 }
522
523 return fault;
524 }
525}};
526
527def template LoadCompleteAcc {{
528 Fault %(class_name)s::completeAcc(PacketPtr pkt,

--- 719 unchanged lines hidden --- 		530 }
531
532 return fault;
533 }
534}};
535
536def template LoadCompleteAcc {{
537 Fault %(class_name)s::completeAcc(PacketPtr pkt,

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