mem.isa (7724:ba11187e2582) | mem.isa (7848:cc5e64f8423f) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 899 unchanged lines hidden (view full) --- 908 909def template RfeConstructor {{ 910 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 911 uint32_t _base, int _mode, bool _wb) 912 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 913 (IntRegIndex)_base, (AddrMode)_mode, _wb) 914 { 915 %(constructor)s; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 899 unchanged lines hidden (view full) --- 908 909def template RfeConstructor {{ 910 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 911 uint32_t _base, int _mode, bool _wb) 912 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 913 (IntRegIndex)_base, (AddrMode)_mode, _wb) 914 { 915 %(constructor)s; |
916 if (!(condCode == COND_AL || condCode == COND_UC)) { 917 for (int x = 0; x < _numDestRegs; x++) { 918 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 919 } 920 } |
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916#if %(use_uops)d 917 assert(numMicroops >= 2); 918 uops = new StaticInstPtr[numMicroops]; 919 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); 920 uops[0]->setDelayedCommit(); 921 uops[1] = new %(wb_decl)s; 922 uops[1]->setLastMicroop(); 923#endif 924 } 925}}; 926 927def template SrsConstructor {{ 928 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 929 uint32_t _regMode, int _mode, bool _wb) 930 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 931 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 932 { 933 %(constructor)s; | 921#if %(use_uops)d 922 assert(numMicroops >= 2); 923 uops = new StaticInstPtr[numMicroops]; 924 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); 925 uops[0]->setDelayedCommit(); 926 uops[1] = new %(wb_decl)s; 927 uops[1]->setLastMicroop(); 928#endif 929 } 930}}; 931 932def template SrsConstructor {{ 933 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 934 uint32_t _regMode, int _mode, bool _wb) 935 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 936 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 937 { 938 %(constructor)s; |
939 if (!(condCode == COND_AL || condCode == COND_UC)) { 940 for (int x = 0; x < _numDestRegs; x++) { 941 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 942 } 943 } |
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934#if %(use_uops)d 935 assert(numMicroops >= 2); 936 uops = new StaticInstPtr[numMicroops]; 937 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 938 uops[0]->setDelayedCommit(); 939 uops[1] = new %(wb_decl)s; 940 uops[1]->setLastMicroop(); 941#endif 942 } 943}}; 944 945def template SwapConstructor {{ 946 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 947 uint32_t _dest, uint32_t _op1, uint32_t _base) 948 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 949 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 950 { 951 %(constructor)s; | 944#if %(use_uops)d 945 assert(numMicroops >= 2); 946 uops = new StaticInstPtr[numMicroops]; 947 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 948 uops[0]->setDelayedCommit(); 949 uops[1] = new %(wb_decl)s; 950 uops[1]->setLastMicroop(); 951#endif 952 } 953}}; 954 955def template SwapConstructor {{ 956 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 957 uint32_t _dest, uint32_t _op1, uint32_t _base) 958 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 959 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 960 { 961 %(constructor)s; |
962 if (!(condCode == COND_AL || condCode == COND_UC)) { 963 for (int x = 0; x < _numDestRegs; x++) { 964 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 965 } 966 } |
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952 } 953}}; 954 955def template LoadStoreDImmConstructor {{ 956 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 957 uint32_t _dest, uint32_t _dest2, 958 uint32_t _base, bool _add, int32_t _imm) 959 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 960 (IntRegIndex)_dest, (IntRegIndex)_dest2, 961 (IntRegIndex)_base, _add, _imm) 962 { 963 %(constructor)s; | 967 } 968}}; 969 970def template LoadStoreDImmConstructor {{ 971 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 972 uint32_t _dest, uint32_t _dest2, 973 uint32_t _base, bool _add, int32_t _imm) 974 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 975 (IntRegIndex)_dest, (IntRegIndex)_dest2, 976 (IntRegIndex)_base, _add, _imm) 977 { 978 %(constructor)s; |
979 if (!(condCode == COND_AL || condCode == COND_UC)) { 980 for (int x = 0; x < _numDestRegs; x++) { 981 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 982 } 983 } |
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964#if %(use_uops)d 965 assert(numMicroops >= 2); 966 uops = new StaticInstPtr[numMicroops]; 967 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 968 uops[0]->setDelayedCommit(); 969 uops[1] = new %(wb_decl)s; 970 uops[1]->setLastMicroop(); 971#endif --- 5 unchanged lines hidden (view full) --- 977 uint32_t _result, uint32_t _dest, uint32_t _dest2, 978 uint32_t _base, bool _add, int32_t _imm) 979 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 980 (IntRegIndex)_result, 981 (IntRegIndex)_dest, (IntRegIndex)_dest2, 982 (IntRegIndex)_base, _add, _imm) 983 { 984 %(constructor)s; | 984#if %(use_uops)d 985 assert(numMicroops >= 2); 986 uops = new StaticInstPtr[numMicroops]; 987 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 988 uops[0]->setDelayedCommit(); 989 uops[1] = new %(wb_decl)s; 990 uops[1]->setLastMicroop(); 991#endif --- 5 unchanged lines hidden (view full) --- 997 uint32_t _result, uint32_t _dest, uint32_t _dest2, 998 uint32_t _base, bool _add, int32_t _imm) 999 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1000 (IntRegIndex)_result, 1001 (IntRegIndex)_dest, (IntRegIndex)_dest2, 1002 (IntRegIndex)_base, _add, _imm) 1003 { 1004 %(constructor)s; |
1005 if (!(condCode == COND_AL || condCode == COND_UC)) { 1006 for (int x = 0; x < _numDestRegs; x++) { 1007 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1008 } 1009 } |
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985#if %(use_uops)d 986 assert(numMicroops >= 2); 987 uops = new StaticInstPtr[numMicroops]; 988 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 989 _base, _add, _imm); 990 uops[0]->setDelayedCommit(); 991 uops[1] = new %(wb_decl)s; 992 uops[1]->setLastMicroop(); 993#endif 994 } 995}}; 996 997def template LoadStoreImmConstructor {{ 998 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 999 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1001 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1002 { 1003 %(constructor)s; | 1010#if %(use_uops)d 1011 assert(numMicroops >= 2); 1012 uops = new StaticInstPtr[numMicroops]; 1013 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 1014 _base, _add, _imm); 1015 uops[0]->setDelayedCommit(); 1016 uops[1] = new %(wb_decl)s; 1017 uops[1]->setLastMicroop(); 1018#endif 1019 } 1020}}; 1021 1022def template LoadStoreImmConstructor {{ 1023 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1024 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1025 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1026 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1027 { 1028 %(constructor)s; |
1029 if (!(condCode == COND_AL || condCode == COND_UC)) { 1030 for (int x = 0; x < _numDestRegs; x++) { 1031 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1032 } 1033 } |
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1004#if %(use_uops)d 1005 assert(numMicroops >= 2); 1006 uops = new StaticInstPtr[numMicroops]; 1007 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 1008 uops[0]->setDelayedCommit(); 1009 uops[1] = new %(wb_decl)s; 1010 uops[1]->setLastMicroop(); 1011#endif --- 4 unchanged lines hidden (view full) --- 1016 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1017 uint32_t _result, uint32_t _dest, uint32_t _base, 1018 bool _add, int32_t _imm) 1019 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1020 (IntRegIndex)_result, (IntRegIndex)_dest, 1021 (IntRegIndex)_base, _add, _imm) 1022 { 1023 %(constructor)s; | 1034#if %(use_uops)d 1035 assert(numMicroops >= 2); 1036 uops = new StaticInstPtr[numMicroops]; 1037 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 1038 uops[0]->setDelayedCommit(); 1039 uops[1] = new %(wb_decl)s; 1040 uops[1]->setLastMicroop(); 1041#endif --- 4 unchanged lines hidden (view full) --- 1046 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1047 uint32_t _result, uint32_t _dest, uint32_t _base, 1048 bool _add, int32_t _imm) 1049 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1050 (IntRegIndex)_result, (IntRegIndex)_dest, 1051 (IntRegIndex)_base, _add, _imm) 1052 { 1053 %(constructor)s; |
1054 if (!(condCode == COND_AL || condCode == COND_UC)) { 1055 for (int x = 0; x < _numDestRegs; x++) { 1056 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1057 } 1058 } |
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1024#if %(use_uops)d 1025 assert(numMicroops >= 2); 1026 uops = new StaticInstPtr[numMicroops]; 1027 uops[0] = new %(acc_name)s(machInst, _result, _dest, 1028 _base, _add, _imm); 1029 uops[0]->setDelayedCommit(); 1030 uops[1] = new %(wb_decl)s; 1031 uops[1]->setLastMicroop(); --- 7 unchanged lines hidden (view full) --- 1039 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1040 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1041 (IntRegIndex)_dest, (IntRegIndex)_dest2, 1042 (IntRegIndex)_base, _add, 1043 _shiftAmt, (ArmShiftType)_shiftType, 1044 (IntRegIndex)_index) 1045 { 1046 %(constructor)s; | 1059#if %(use_uops)d 1060 assert(numMicroops >= 2); 1061 uops = new StaticInstPtr[numMicroops]; 1062 uops[0] = new %(acc_name)s(machInst, _result, _dest, 1063 _base, _add, _imm); 1064 uops[0]->setDelayedCommit(); 1065 uops[1] = new %(wb_decl)s; 1066 uops[1]->setLastMicroop(); --- 7 unchanged lines hidden (view full) --- 1074 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1075 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1076 (IntRegIndex)_dest, (IntRegIndex)_dest2, 1077 (IntRegIndex)_base, _add, 1078 _shiftAmt, (ArmShiftType)_shiftType, 1079 (IntRegIndex)_index) 1080 { 1081 %(constructor)s; |
1082 if (!(condCode == COND_AL || condCode == COND_UC)) { 1083 for (int x = 0; x < _numDestRegs; x++) { 1084 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1085 } 1086 } |
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1047#if %(use_uops)d 1048 assert(numMicroops >= 2); 1049 uops = new StaticInstPtr[numMicroops]; 1050 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 1051 _shiftAmt, _shiftType, _index); 1052 uops[0]->setDelayedCommit(); 1053 uops[1] = new %(wb_decl)s; 1054 uops[1]->setLastMicroop(); --- 6 unchanged lines hidden (view full) --- 1061 uint32_t _dest, uint32_t _base, bool _add, 1062 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1063 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1064 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1065 _shiftAmt, (ArmShiftType)_shiftType, 1066 (IntRegIndex)_index) 1067 { 1068 %(constructor)s; | 1087#if %(use_uops)d 1088 assert(numMicroops >= 2); 1089 uops = new StaticInstPtr[numMicroops]; 1090 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 1091 _shiftAmt, _shiftType, _index); 1092 uops[0]->setDelayedCommit(); 1093 uops[1] = new %(wb_decl)s; 1094 uops[1]->setLastMicroop(); --- 6 unchanged lines hidden (view full) --- 1101 uint32_t _dest, uint32_t _base, bool _add, 1102 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1103 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1104 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1105 _shiftAmt, (ArmShiftType)_shiftType, 1106 (IntRegIndex)_index) 1107 { 1108 %(constructor)s; |
1109 if (!(condCode == COND_AL || condCode == COND_UC)) { 1110 for (int x = 0; x < _numDestRegs; x++) { 1111 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1112 } 1113 } |
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1069#if %(use_uops)d 1070 assert(numMicroops >= 2); 1071 uops = new StaticInstPtr[numMicroops]; 1072 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 1073 _shiftAmt, _shiftType, _index); 1074 uops[0]->setDelayedCommit(); 1075 uops[1] = new %(wb_decl)s; 1076 uops[1]->setLastMicroop(); --- 7 unchanged lines hidden (view full) --- 1084 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1085 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1086 (IntRegIndex)_dest, (IntRegIndex)_dest2, 1087 (IntRegIndex)_base, _add, 1088 _shiftAmt, (ArmShiftType)_shiftType, 1089 (IntRegIndex)_index) 1090 { 1091 %(constructor)s; | 1114#if %(use_uops)d 1115 assert(numMicroops >= 2); 1116 uops = new StaticInstPtr[numMicroops]; 1117 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 1118 _shiftAmt, _shiftType, _index); 1119 uops[0]->setDelayedCommit(); 1120 uops[1] = new %(wb_decl)s; 1121 uops[1]->setLastMicroop(); --- 7 unchanged lines hidden (view full) --- 1129 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1131 (IntRegIndex)_dest, (IntRegIndex)_dest2, 1132 (IntRegIndex)_base, _add, 1133 _shiftAmt, (ArmShiftType)_shiftType, 1134 (IntRegIndex)_index) 1135 { 1136 %(constructor)s; |
1137 if (!(condCode == COND_AL || condCode == COND_UC)) { 1138 for (int x = 0; x < _numDestRegs; x++) { 1139 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1140 } 1141 } |
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1092#if %(use_uops)d 1093 assert(numMicroops >= 2); 1094 uops = new StaticInstPtr[numMicroops]; 1095 if ((_dest == _index) || (_dest2 == _index)) { 1096 IntRegIndex wbIndexReg = INTREG_UREG0; 1097 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 1098 uops[0]->setDelayedCommit(); 1099 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, --- 18 unchanged lines hidden (view full) --- 1118 uint32_t _dest, uint32_t _base, bool _add, 1119 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1121 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1122 _shiftAmt, (ArmShiftType)_shiftType, 1123 (IntRegIndex)_index) 1124 { 1125 %(constructor)s; | 1142#if %(use_uops)d 1143 assert(numMicroops >= 2); 1144 uops = new StaticInstPtr[numMicroops]; 1145 if ((_dest == _index) || (_dest2 == _index)) { 1146 IntRegIndex wbIndexReg = INTREG_UREG0; 1147 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 1148 uops[0]->setDelayedCommit(); 1149 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, --- 18 unchanged lines hidden (view full) --- 1168 uint32_t _dest, uint32_t _base, bool _add, 1169 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1170 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1171 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1172 _shiftAmt, (ArmShiftType)_shiftType, 1173 (IntRegIndex)_index) 1174 { 1175 %(constructor)s; |
1176 if (!(condCode == COND_AL || condCode == COND_UC)) { 1177 for (int x = 0; x < _numDestRegs; x++) { 1178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1179 } 1180 } |
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1126#if %(use_uops)d 1127 assert(numMicroops >= 2); 1128 uops = new StaticInstPtr[numMicroops]; 1129 if (_dest == INTREG_PC) { 1130 IntRegIndex wbIndexReg = index; 1131 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1132 _shiftAmt, _shiftType, _index); 1133 uops[0]->setDelayedCommit(); --- 25 unchanged lines hidden (view full) --- 1159 1160def template LoadImmConstructor {{ 1161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1162 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1163 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1164 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1165 { 1166 %(constructor)s; | 1181#if %(use_uops)d 1182 assert(numMicroops >= 2); 1183 uops = new StaticInstPtr[numMicroops]; 1184 if (_dest == INTREG_PC) { 1185 IntRegIndex wbIndexReg = index; 1186 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1187 _shiftAmt, _shiftType, _index); 1188 uops[0]->setDelayedCommit(); --- 25 unchanged lines hidden (view full) --- 1214 1215def template LoadImmConstructor {{ 1216 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1217 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1218 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1219 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1220 { 1221 %(constructor)s; |
1222 if (!(condCode == COND_AL || condCode == COND_UC)) { 1223 for (int x = 0; x < _numDestRegs; x++) { 1224 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1225 } 1226 } |
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1167#if %(use_uops)d 1168 assert(numMicroops >= 2); 1169 uops = new StaticInstPtr[numMicroops]; 1170 if (_dest == INTREG_PC) { 1171 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1172 _imm); 1173 uops[0]->setDelayedCommit(); 1174 uops[1] = new %(wb_decl)s; --- 13 unchanged lines hidden --- | 1227#if %(use_uops)d 1228 assert(numMicroops >= 2); 1229 uops = new StaticInstPtr[numMicroops]; 1230 if (_dest == INTREG_PC) { 1231 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1232 _imm); 1233 uops[0]->setDelayedCommit(); 1234 uops[1] = new %(wb_decl)s; --- 13 unchanged lines hidden --- |