mem.isa (7711:fe91d5e2c374) | mem.isa (7712:7733c562e5e3) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 581 unchanged lines hidden (view full) --- 590 } 591}}; 592 593def template StoreCompleteAcc {{ 594 Fault %(class_name)s::completeAcc(PacketPtr pkt, 595 %(CPU_exec_context)s *xc, 596 Trace::InstRecord *traceData) const 597 { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 581 unchanged lines hidden (view full) --- 590 } 591}}; 592 593def template StoreCompleteAcc {{ 594 Fault %(class_name)s::completeAcc(PacketPtr pkt, 595 %(CPU_exec_context)s *xc, 596 Trace::InstRecord *traceData) const 597 { |
598 Fault fault = NoFault; 599 600 %(op_decl)s; 601 %(op_rd)s; 602 603 if (%(predicate_test)s) 604 { 605 if (fault == NoFault) { 606 %(op_wb)s; 607 } 608 } 609 610 if (fault == NoFault && machInst.itstateMask != 0) { | 598 if (machInst.itstateMask != 0) { 599 warn_once("Complete acc isn't called on normal stores in O3."); |
611 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 612 } | 600 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 601 } |
613 614 return fault; | 602 return NoFault; |
615 } 616}}; 617 618def template NeonStoreCompleteAcc {{ 619 template <class Element> 620 Fault %(class_name)s<Element>::completeAcc( 621 PacketPtr pkt, %(CPU_exec_context)s *xc, 622 Trace::InstRecord *traceData) const 623 { | 603 } 604}}; 605 606def template NeonStoreCompleteAcc {{ 607 template <class Element> 608 Fault %(class_name)s<Element>::completeAcc( 609 PacketPtr pkt, %(CPU_exec_context)s *xc, 610 Trace::InstRecord *traceData) const 611 { |
624 Fault fault = NoFault; 625 626 %(op_decl)s; 627 %(op_rd)s; 628 629 if (%(predicate_test)s) 630 { 631 if (fault == NoFault) { 632 %(op_wb)s; 633 } 634 } 635 636 if (fault == NoFault && machInst.itstateMask != 0) { | 612 if (machInst.itstateMask != 0) { 613 warn_once("Complete acc isn't called on normal stores in O3."); |
637 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 638 } | 614 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 615 } |
639 640 return fault; | 616 return NoFault; |
641 } 642}}; 643 644def template StoreExCompleteAcc {{ 645 Fault %(class_name)s::completeAcc(PacketPtr pkt, 646 %(CPU_exec_context)s *xc, 647 Trace::InstRecord *traceData) const 648 { --- 544 unchanged lines hidden --- | 617 } 618}}; 619 620def template StoreExCompleteAcc {{ 621 Fault %(class_name)s::completeAcc(PacketPtr pkt, 622 %(CPU_exec_context)s *xc, 623 Trace::InstRecord *traceData) const 624 { --- 544 unchanged lines hidden --- |