mem.isa (7646:a444dbee8c07) mem.isa (7711:fe91d5e2c374)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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126 if (%(predicate_test)s)
127 {
128 %(preacc_code)s;
129
130 if (fault == NoFault) {
131 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
132 memAccessFlags, &memData);
133 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 117 unchanged lines hidden (view full) ---

126 if (%(predicate_test)s)
127 {
128 %(preacc_code)s;
129
130 if (fault == NoFault) {
131 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
132 memAccessFlags, &memData);
133 }
134
135 if (fault == NoFault) {
136 %(op_wb)s;
137 }
138 } else {
139 xc->setPredicate(false);
140 }
141
142 if (fault == NoFault && machInst.itstateMask != 0 &&
143 (!isMicroop() || isLastMicroop())) {
144 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
145 }

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388 if (fault == NoFault) {
389 %(memacc_code)s;
390 }
391
392 if (fault == NoFault) {
393 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
394 memAccessFlags, NULL);
395 }
134 } else {
135 xc->setPredicate(false);
136 }
137
138 if (fault == NoFault && machInst.itstateMask != 0 &&
139 (!isMicroop() || isLastMicroop())) {
140 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
141 }

--- 242 unchanged lines hidden (view full) ---

384 if (fault == NoFault) {
385 %(memacc_code)s;
386 }
387
388 if (fault == NoFault) {
389 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
390 memAccessFlags, NULL);
391 }
396
397 // Need to write back any potential address register update
398 if (fault == NoFault) {
399 %(op_wb)s;
400 }
401 } else {
402 xc->setPredicate(false);
403 }
404 if (fault == NoFault && machInst.itstateMask != 0 &&
405 (!isMicroop() || isLastMicroop())) {
406 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
407 }
408

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426 if (fault == NoFault) {
427 %(memacc_code)s;
428 }
429
430 if (fault == NoFault) {
431 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
432 memAccessFlags, NULL);
433 }
392 } else {
393 xc->setPredicate(false);
394 }
395 if (fault == NoFault && machInst.itstateMask != 0 &&
396 (!isMicroop() || isLastMicroop())) {
397 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
398 }
399

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417 if (fault == NoFault) {
418 %(memacc_code)s;
419 }
420
421 if (fault == NoFault) {
422 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
423 memAccessFlags, NULL);
424 }
434
435 // Need to write back any potential address register update
436 if (fault == NoFault) {
437 %(op_wb)s;
438 }
439 } else {
440 xc->setPredicate(false);
441 }
442
443 if (fault == NoFault && machInst.itstateMask != 0 &&
444 (!isMicroop() || isLastMicroop())) {
445 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
446 }

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468 if (fault == NoFault) {
469 %(memacc_code)s;
470 }
471
472 if (fault == NoFault) {
473 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
474 memAccessFlags, NULL);
475 }
425 } else {
426 xc->setPredicate(false);
427 }
428
429 if (fault == NoFault && machInst.itstateMask != 0 &&
430 (!isMicroop() || isLastMicroop())) {
431 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
432 }

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454 if (fault == NoFault) {
455 %(memacc_code)s;
456 }
457
458 if (fault == NoFault) {
459 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
460 memAccessFlags, NULL);
461 }
476
477 // Need to write back any potential address register update
478 if (fault == NoFault) {
479 %(op_wb)s;
480 }
481 }
482
483 if (fault == NoFault && machInst.itstateMask != 0 &&
484 (!isMicroop() || isLastMicroop())) {
485 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
486 }
487
488 return fault;

--- 723 unchanged lines hidden --- 		462 }
463
464 if (fault == NoFault && machInst.itstateMask != 0 &&
465 (!isMicroop() || isLastMicroop())) {
466 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
467 }
468
469 return fault;

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