mem.isa (7639:8c09b7ff5b57) mem.isa (7646:a444dbee8c07)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template PanicExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 panic("Execute function executed when it shouldn't be!\n");
49 return NoFault;
50 }
51}};
52
53def template PanicInitiateAcc {{
54 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
55 Trace::InstRecord *traceData) const
56 {
57 panic("InitiateAcc function executed when it shouldn't be!\n");
58 return NoFault;
59 }
60}};
61
62def template PanicCompleteAcc {{
63 Fault %(class_name)s::completeAcc(PacketPtr pkt,
64 %(CPU_exec_context)s *xc,
65 Trace::InstRecord *traceData) const
66 {
67 panic("CompleteAcc function executed when it shouldn't be!\n");
68 return NoFault;
69 }
70}};
71
72
44def template SwapExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;

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68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 } else {
73 xc->setPredicate(false);
74 }
75
73def template SwapExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Addr EA;
78 Fault fault = NoFault;
79
80 %(op_decl)s;

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97
98 if (fault == NoFault) {
99 %(op_wb)s;
100 }
101 } else {
102 xc->setPredicate(false);
103 }
104
76 if (fault == NoFault && machInst.itstateMask != 0) {
105 if (fault == NoFault && machInst.itstateMask != 0 &&
106 (!isMicroop() || isLastMicroop())) {
77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
78 }
79
80 return fault;
81 }
82}};
83
84def template SwapInitiateAcc {{

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104
105 if (fault == NoFault) {
106 %(op_wb)s;
107 }
108 } else {
109 xc->setPredicate(false);
110 }
111
107 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
108 }
109
110 return fault;
111 }
112}};
113
114def template SwapInitiateAcc {{

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134
135 if (fault == NoFault) {
136 %(op_wb)s;
137 }
138 } else {
139 xc->setPredicate(false);
140 }
141
112 if (fault == NoFault && machInst.itstateMask != 0) {
142 if (fault == NoFault && machInst.itstateMask != 0 &&
143 (!isMicroop() || isLastMicroop())) {
113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
114 }
115
116 return fault;
117 }
118}};
119
120def template SwapCompleteAcc {{

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167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 } else {
172 xc->setPredicate(false);
173 }
174
144 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
145 }
146
147 return fault;
148 }
149}};
150
151def template SwapCompleteAcc {{

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198
199 if (fault == NoFault) {
200 %(op_wb)s;
201 }
202 } else {
203 xc->setPredicate(false);
204 }
205
175 if (fault == NoFault && machInst.itstateMask != 0) {
206 if (fault == NoFault && machInst.itstateMask != 0 &&
207 (!isMicroop() || isLastMicroop())) {
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }
181}};
182
183def template NeonLoadExecute {{

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203 %(memacc_code)s;
204 }
205
206 if (fault == NoFault) {
207 %(op_wb)s;
208 }
209 }
210
208 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
209 }
210
211 return fault;
212 }
213}};
214
215def template NeonLoadExecute {{

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235 %(memacc_code)s;
236 }
237
238 if (fault == NoFault) {
239 %(op_wb)s;
240 }
241 }
242
211 if (fault == NoFault && machInst.itstateMask != 0) {
243 if (fault == NoFault && machInst.itstateMask != 0 &&
244 (!isMicroop() || isLastMicroop())) {
212 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
213 }
214
215 return fault;
216 }
217}};
218
219def template StoreExecute {{

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240
241 if (fault == NoFault) {
242 %(op_wb)s;
243 }
244 } else {
245 xc->setPredicate(false);
246 }
247
245 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
246 }
247
248 return fault;
249 }
250}};
251
252def template StoreExecute {{

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273
274 if (fault == NoFault) {
275 %(op_wb)s;
276 }
277 } else {
278 xc->setPredicate(false);
279 }
280
248 if (fault == NoFault && machInst.itstateMask != 0) {
281 if (fault == NoFault && machInst.itstateMask != 0 &&
282 (!isMicroop() || isLastMicroop())) {
249 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
250 }
251
252 return fault;
253 }
254}};
255
256def template NeonStoreExecute {{

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280 memAccessFlags, NULL);
281 }
282
283 if (fault == NoFault) {
284 %(op_wb)s;
285 }
286 }
287
283 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
284 }
285
286 return fault;
287 }
288}};
289
290def template NeonStoreExecute {{

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314 memAccessFlags, NULL);
315 }
316
317 if (fault == NoFault) {
318 %(op_wb)s;
319 }
320 }
321
288 if (fault == NoFault && machInst.itstateMask != 0) {
322 if (fault == NoFault && machInst.itstateMask != 0 &&
323 (!isMicroop() || isLastMicroop())) {
289 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
290 }
291
292 return fault;
293 }
294}};
295
296def template StoreExExecute {{

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323
324 if (fault == NoFault) {
325 %(op_wb)s;
326 }
327 } else {
328 xc->setPredicate(false);
329 }
330
324 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
325 }
326
327 return fault;
328 }
329}};
330
331def template StoreExExecute {{

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358
359 if (fault == NoFault) {
360 %(op_wb)s;
361 }
362 } else {
363 xc->setPredicate(false);
364 }
365
331 if (fault == NoFault && machInst.itstateMask != 0) {
366 if (fault == NoFault && machInst.itstateMask != 0 &&
367 (!isMicroop() || isLastMicroop())) {
332 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
333 }
334
335 return fault;
336 }
337}};
338
339def template StoreExInitiateAcc {{

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360
361 // Need to write back any potential address register update
362 if (fault == NoFault) {
363 %(op_wb)s;
364 }
365 } else {
366 xc->setPredicate(false);
367 }
368 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
369 }
370
371 return fault;
372 }
373}};
374
375def template StoreExInitiateAcc {{

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396
397 // Need to write back any potential address register update
398 if (fault == NoFault) {
399 %(op_wb)s;
400 }
401 } else {
402 xc->setPredicate(false);
403 }
368
369 if (fault == NoFault && machInst.itstateMask != 0) {
404 if (fault == NoFault && machInst.itstateMask != 0 &&
405 (!isMicroop() || isLastMicroop())) {
370 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
371 }
372
373 return fault;
374 }
375}};
376
377def template StoreInitiateAcc {{

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399 // Need to write back any potential address register update
400 if (fault == NoFault) {
401 %(op_wb)s;
402 }
403 } else {
404 xc->setPredicate(false);
405 }
406
406 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
407 }
408
409 return fault;
410 }
411}};
412
413def template StoreInitiateAcc {{

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435 // Need to write back any potential address register update
436 if (fault == NoFault) {
437 %(op_wb)s;
438 }
439 } else {
440 xc->setPredicate(false);
441 }
442
407 if (fault == NoFault && machInst.itstateMask != 0) {
443 if (fault == NoFault && machInst.itstateMask != 0 &&
444 (!isMicroop() || isLastMicroop())) {
408 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
409 }
410
411 return fault;
412 }
413}};
414
415def template NeonStoreInitiateAcc {{

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438 }
439
440 // Need to write back any potential address register update
441 if (fault == NoFault) {
442 %(op_wb)s;
443 }
444 }
445
445 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
446 }
447
448 return fault;
449 }
450}};
451
452def template NeonStoreInitiateAcc {{

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475 }
476
477 // Need to write back any potential address register update
478 if (fault == NoFault) {
479 %(op_wb)s;
480 }
481 }
482
446 if (fault == NoFault && machInst.itstateMask != 0) {
483 if (fault == NoFault && machInst.itstateMask != 0 &&
484 (!isMicroop() || isLastMicroop())) {
447 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
448 }
449
450 return fault;
451 }
452}};
453
454def template LoadInitiateAcc {{

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464
465 if (%(predicate_test)s)
466 {
467 if (fault == NoFault) {
468 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
469 }
470 } else {
471 xc->setPredicate(false);
485 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
486 }
487
488 return fault;
489 }
490}};
491
492def template LoadInitiateAcc {{

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502
503 if (%(predicate_test)s)
504 {
505 if (fault == NoFault) {
506 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
507 }
508 } else {
509 xc->setPredicate(false);
472 if (fault == NoFault && machInst.itstateMask != 0) {
510 if (fault == NoFault && machInst.itstateMask != 0 &&
511 (!isMicroop() || isLastMicroop())) {
473 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
474 }
475 }
476
477 return fault;
478 }
479}};
480

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490 %(op_rd)s;
491 %(ea_code)s;
492
493 if (%(predicate_test)s)
494 {
495 if (fault == NoFault) {
496 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
497 }
512 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
513 }
514 }
515
516 return fault;
517 }
518}};
519

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529 %(op_rd)s;
530 %(ea_code)s;
531
532 if (%(predicate_test)s)
533 {
534 if (fault == NoFault) {
535 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
536 }
498 } else if (fault == NoFault && machInst.itstateMask != 0) {
537 } else if (fault == NoFault && machInst.itstateMask != 0 &&
538 (!isMicroop() || isLastMicroop())) {
499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
500 }
501
502 return fault;
503 }
504}};
505
506def template LoadCompleteAcc {{

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786 %(BasicExecDeclare)s
787
788 %(InitiateAccDeclare)s
789
790 %(CompleteAccDeclare)s
791 };
792}};
793
539 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
540 }
541
542 return fault;
543 }
544}};
545
546def template LoadCompleteAcc {{

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826 %(BasicExecDeclare)s
827
828 %(InitiateAccDeclare)s
829
830 %(CompleteAccDeclare)s
831 };
832}};
833
794def template LoadStoreDRegDeclare {{
834def template StoreDRegDeclare {{
795 /**
796 * Static instruction class for "%(mnemonic)s".
797 */
798 class %(class_name)s : public %(base_class)s
799 {
800 public:
801
802 /// Constructor.

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809 %(BasicExecDeclare)s
810
811 %(InitiateAccDeclare)s
812
813 %(CompleteAccDeclare)s
814 };
815}};
816
835 /**
836 * Static instruction class for "%(mnemonic)s".
837 */
838 class %(class_name)s : public %(base_class)s
839 {
840 public:
841
842 /// Constructor.

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849 %(BasicExecDeclare)s
850
851 %(InitiateAccDeclare)s
852
853 %(CompleteAccDeclare)s
854 };
855}};
856
817def template LoadStoreRegDeclare {{
857def template StoreRegDeclare {{
818 /**
819 * Static instruction class for "%(mnemonic)s".
820 */
821 class %(class_name)s : public %(base_class)s
822 {
823 public:
824
825 /// Constructor.

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831 %(BasicExecDeclare)s
832
833 %(InitiateAccDeclare)s
834
835 %(CompleteAccDeclare)s
836 };
837}};
838
858 /**
859 * Static instruction class for "%(mnemonic)s".
860 */
861 class %(class_name)s : public %(base_class)s
862 {
863 public:
864
865 /// Constructor.

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871 %(BasicExecDeclare)s
872
873 %(InitiateAccDeclare)s
874
875 %(CompleteAccDeclare)s
876 };
877}};
878
879def template LoadDRegDeclare {{
880 /**
881 * Static instruction class for "%(mnemonic)s".
882 */
883 class %(class_name)s : public %(base_class)s
884 {
885 public:
886
887 /// Constructor.
888 %(class_name)s(ExtMachInst machInst,
889 uint32_t _dest, uint32_t _dest2,
890 uint32_t _base, bool _add,
891 int32_t _shiftAmt, uint32_t _shiftType,
892 uint32_t _index);
893
894 %(BasicExecDeclare)s
895
896 %(InitiateAccDeclare)s
897
898 %(CompleteAccDeclare)s
899 };
900}};
901
902def template LoadRegDeclare {{
903 /**
904 * Static instruction class for "%(mnemonic)s".
905 */
906 class %(class_name)s : public %(base_class)s
907 {
908 public:
909
910 /// Constructor.
911 %(class_name)s(ExtMachInst machInst,
912 uint32_t _dest, uint32_t _base, bool _add,
913 int32_t _shiftAmt, uint32_t _shiftType,
914 uint32_t _index);
915
916 %(BasicExecDeclare)s
917
918 %(InitiateAccDeclare)s
919
920 %(CompleteAccDeclare)s
921 };
922}};
923
924def template LoadImmDeclare {{
925 /**
926 * Static instruction class for "%(mnemonic)s".
927 */
928 class %(class_name)s : public %(base_class)s
929 {
930 public:
931
932 /// Constructor.
933 %(class_name)s(ExtMachInst machInst,
934 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
935
936 %(BasicExecDeclare)s
937
938 %(InitiateAccDeclare)s
939
940 %(CompleteAccDeclare)s
941 };
942}};
943
839def template InitiateAccDeclare {{
840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
841}};
842
843def template CompleteAccDeclare {{
844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
845}};
846
847def template RfeConstructor {{
848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 uint32_t _base, int _mode, bool _wb)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 (IntRegIndex)_base, (AddrMode)_mode, _wb)
852 {
853 %(constructor)s;
944def template InitiateAccDeclare {{
945 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
946}};
947
948def template CompleteAccDeclare {{
949 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
950}};
951
952def template RfeConstructor {{
953 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
954 uint32_t _base, int _mode, bool _wb)
955 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
956 (IntRegIndex)_base, (AddrMode)_mode, _wb)
957 {
958 %(constructor)s;
959#if %(use_uops)d
960 assert(numMicroops >= 2);
961 uops = new StaticInstPtr[numMicroops];
962 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
963 uops[1] = new %(wb_decl)s;
964 uops[1]->setLastMicroop();
965#endif
854 }
855}};
856
857def template SrsConstructor {{
858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
859 uint32_t _regMode, int _mode, bool _wb)
860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
861 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
862 {
863 %(constructor)s;
966 }
967}};
968
969def template SrsConstructor {{
970 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
971 uint32_t _regMode, int _mode, bool _wb)
972 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
973 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
974 {
975 %(constructor)s;
976#if %(use_uops)d
977 assert(numMicroops >= 2);
978 uops = new StaticInstPtr[numMicroops];
979 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
980 uops[1] = new %(wb_decl)s;
981 uops[1]->setLastMicroop();
982#endif
864 }
865}};
866
867def template SwapConstructor {{
868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
869 uint32_t _dest, uint32_t _op1, uint32_t _base)
870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)

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878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
879 uint32_t _dest, uint32_t _dest2,
880 uint32_t _base, bool _add, int32_t _imm)
881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
882 (IntRegIndex)_dest, (IntRegIndex)_dest2,
883 (IntRegIndex)_base, _add, _imm)
884 {
885 %(constructor)s;
983 }
984}};
985
986def template SwapConstructor {{
987 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
988 uint32_t _dest, uint32_t _op1, uint32_t _base)
989 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
990 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)

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997 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
998 uint32_t _dest, uint32_t _dest2,
999 uint32_t _base, bool _add, int32_t _imm)
1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1001 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1002 (IntRegIndex)_base, _add, _imm)
1003 {
1004 %(constructor)s;
1005#if %(use_uops)d
1006 assert(numMicroops >= 2);
1007 uops = new StaticInstPtr[numMicroops];
1008 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
1009 uops[1] = new %(wb_decl)s;
1010 uops[1]->setLastMicroop();
1011#endif
886 }
887}};
888
889def template StoreExDImmConstructor {{
890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
891 uint32_t _result, uint32_t _dest, uint32_t _dest2,
892 uint32_t _base, bool _add, int32_t _imm)
893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
894 (IntRegIndex)_result,
895 (IntRegIndex)_dest, (IntRegIndex)_dest2,
896 (IntRegIndex)_base, _add, _imm)
897 {
898 %(constructor)s;
1012 }
1013}};
1014
1015def template StoreExDImmConstructor {{
1016 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1017 uint32_t _result, uint32_t _dest, uint32_t _dest2,
1018 uint32_t _base, bool _add, int32_t _imm)
1019 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1020 (IntRegIndex)_result,
1021 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1022 (IntRegIndex)_base, _add, _imm)
1023 {
1024 %(constructor)s;
1025#if %(use_uops)d
1026 assert(numMicroops >= 2);
1027 uops = new StaticInstPtr[numMicroops];
1028 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
1029 _base, _add, _imm);
1030 uops[1] = new %(wb_decl)s;
1031 uops[1]->setLastMicroop();
1032#endif
899 }
900}};
901
902def template LoadStoreImmConstructor {{
903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
907 {
908 %(constructor)s;
1033 }
1034}};
1035
1036def template LoadStoreImmConstructor {{
1037 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1038 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1039 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1040 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1041 {
1042 %(constructor)s;
1043#if %(use_uops)d
1044 assert(numMicroops >= 2);
1045 uops = new StaticInstPtr[numMicroops];
1046 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1047 uops[1] = new %(wb_decl)s;
1048 uops[1]->setLastMicroop();
1049#endif
909 }
910}};
911
912def template StoreExImmConstructor {{
913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
914 uint32_t _result, uint32_t _dest, uint32_t _base,
915 bool _add, int32_t _imm)
916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
917 (IntRegIndex)_result, (IntRegIndex)_dest,
918 (IntRegIndex)_base, _add, _imm)
919 {
920 %(constructor)s;
1050 }
1051}};
1052
1053def template StoreExImmConstructor {{
1054 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1055 uint32_t _result, uint32_t _dest, uint32_t _base,
1056 bool _add, int32_t _imm)
1057 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1058 (IntRegIndex)_result, (IntRegIndex)_dest,
1059 (IntRegIndex)_base, _add, _imm)
1060 {
1061 %(constructor)s;
1062#if %(use_uops)d
1063 assert(numMicroops >= 2);
1064 uops = new StaticInstPtr[numMicroops];
1065 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1066 _base, _add, _imm);
1067 uops[1] = new %(wb_decl)s;
1068 uops[1]->setLastMicroop();
1069#endif
921 }
922}};
923
1070 }
1071}};
1072
924def template LoadStoreDRegConstructor {{
1073def template StoreDRegConstructor {{
925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
929 (IntRegIndex)_dest, (IntRegIndex)_dest2,
930 (IntRegIndex)_base, _add,
931 _shiftAmt, (ArmShiftType)_shiftType,
932 (IntRegIndex)_index)
933 {
934 %(constructor)s;
1074 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1075 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1076 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1077 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1078 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1079 (IntRegIndex)_base, _add,
1080 _shiftAmt, (ArmShiftType)_shiftType,
1081 (IntRegIndex)_index)
1082 {
1083 %(constructor)s;
1084#if %(use_uops)d
1085 assert(numMicroops >= 2);
1086 uops = new StaticInstPtr[numMicroops];
1087 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1088 _shiftAmt, _shiftType, _index);
1089 uops[1] = new %(wb_decl)s;
1090 uops[1]->setLastMicroop();
1091#endif
935 }
936}};
937
1092 }
1093}};
1094
938def template LoadStoreRegConstructor {{
1095def template StoreRegConstructor {{
939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
940 uint32_t _dest, uint32_t _base, bool _add,
941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
943 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
944 _shiftAmt, (ArmShiftType)_shiftType,
945 (IntRegIndex)_index)
946 {
947 %(constructor)s;
1096 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1097 uint32_t _dest, uint32_t _base, bool _add,
1098 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1099 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1100 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1101 _shiftAmt, (ArmShiftType)_shiftType,
1102 (IntRegIndex)_index)
1103 {
1104 %(constructor)s;
1105#if %(use_uops)d
1106 assert(numMicroops >= 2);
1107 uops = new StaticInstPtr[numMicroops];
1108 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1109 _shiftAmt, _shiftType, _index);
1110 uops[1] = new %(wb_decl)s;
1111 uops[1]->setLastMicroop();
1112#endif
948 }
949}};
1113 }
1114}};
1115
1116def template LoadDRegConstructor {{
1117 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1118 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1119 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1121 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1122 (IntRegIndex)_base, _add,
1123 _shiftAmt, (ArmShiftType)_shiftType,
1124 (IntRegIndex)_index)
1125 {
1126 %(constructor)s;
1127#if %(use_uops)d
1128 assert(numMicroops >= 2);
1129 uops = new StaticInstPtr[numMicroops];
1130 if ((_dest == _index) || (_dest2 == _index)) {
1131 IntRegIndex wbIndexReg = INTREG_UREG0;
1132 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1133 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1134 _shiftAmt, _shiftType, _index);
1135 uops[2] = new %(wb_decl)s;
1136 uops[2]->setLastMicroop();
1137 } else {
1138 IntRegIndex wbIndexReg = index;
1139 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1140 _shiftAmt, _shiftType, _index);
1141 uops[1] = new %(wb_decl)s;
1142 uops[1]->setLastMicroop();
1143 }
1144#endif
1145 }
1146}};
1147
1148def template LoadRegConstructor {{
1149 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1150 uint32_t _dest, uint32_t _base, bool _add,
1151 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1152 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1153 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1154 _shiftAmt, (ArmShiftType)_shiftType,
1155 (IntRegIndex)_index)
1156 {
1157 %(constructor)s;
1158#if %(use_uops)d
1159 assert(numMicroops >= 2);
1160 uops = new StaticInstPtr[numMicroops];
1161 if (_dest == INTREG_PC) {
1162 IntRegIndex wbIndexReg = index;
1163 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1164 _shiftAmt, _shiftType, _index);
1165 uops[1] = new %(wb_decl)s;
1166 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1167 uops[2]->setLastMicroop();
1168 } else if(_dest == _index) {
1169 IntRegIndex wbIndexReg = INTREG_UREG0;
1170 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1171 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1172 _shiftAmt, _shiftType, _index);
1173 uops[2] = new %(wb_decl)s;
1174 uops[2]->setLastMicroop();
1175 } else {
1176 IntRegIndex wbIndexReg = index;
1177 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1178 _shiftAmt, _shiftType, _index);
1179 uops[1] = new %(wb_decl)s;
1180 uops[1]->setLastMicroop();
1181
1182 }
1183#endif
1184 }
1185}};
1186
1187def template LoadImmConstructor {{
1188 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1189 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1190 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1191 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1192 {
1193 %(constructor)s;
1194#if %(use_uops)d
1195 assert(numMicroops >= 2);
1196 uops = new StaticInstPtr[numMicroops];
1197 if (_dest == INTREG_PC) {
1198 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1199 _imm);
1200 uops[1] = new %(wb_decl)s;
1201 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1202 uops[2]->setLastMicroop();
1203 } else {
1204 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1205 uops[1] = new %(wb_decl)s;
1206 uops[1]->setLastMicroop();
1207 }
1208#endif
1209 }
1210}};
1211