mem.isa (7440:00aa12f63896) mem.isa (7597:063f160e8b50)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

--- 55 unchanged lines hidden (view full) ---

64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 } else {
73 xc->setPredicate(false);
72 }
73
74 if (fault == NoFault && machInst.itstateMask != 0) {
75 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
76 }
77
78 return fault;
79 }

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98 if (fault == NoFault) {
99 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
100 memAccessFlags, &memData);
101 }
102
103 if (fault == NoFault) {
104 %(op_wb)s;
105 }
74 }
75
76 if (fault == NoFault && machInst.itstateMask != 0) {
77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
78 }
79
80 return fault;
81 }

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100 if (fault == NoFault) {
101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
102 memAccessFlags, &memData);
103 }
104
105 if (fault == NoFault) {
106 %(op_wb)s;
107 }
108 } else {
109 xc->setPredicate(false);
106 }
107
108 if (fault == NoFault && machInst.itstateMask != 0) {
109 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
110 }
111
112 return fault;
113 }

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159 if (fault == NoFault) {
160 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
161 %(memacc_code)s;
162 }
163
164 if (fault == NoFault) {
165 %(op_wb)s;
166 }
110 }
111
112 if (fault == NoFault && machInst.itstateMask != 0) {
113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
114 }
115
116 return fault;
117 }

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163 if (fault == NoFault) {
164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
165 %(memacc_code)s;
166 }
167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 } else {
172 xc->setPredicate(false);
167 }
168
169 if (fault == NoFault && machInst.itstateMask != 0) {
170 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
171 }
172
173 return fault;
174 }

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195 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
196 memAccessFlags, NULL);
197 if (traceData) { traceData->setData(Mem); }
198 }
199
200 if (fault == NoFault) {
201 %(op_wb)s;
202 }
173 }
174
175 if (fault == NoFault && machInst.itstateMask != 0) {
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }

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201 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
202 memAccessFlags, NULL);
203 if (traceData) { traceData->setData(Mem); }
204 }
205
206 if (fault == NoFault) {
207 %(op_wb)s;
208 }
209 } else {
210 xc->setPredicate(false);
203 }
204
205 if (fault == NoFault && machInst.itstateMask != 0) {
206 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
207 }
208
209 return fault;
210 }

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237
238 if (fault == NoFault) {
239 %(postacc_code)s;
240 }
241
242 if (fault == NoFault) {
243 %(op_wb)s;
244 }
211 }
212
213 if (fault == NoFault && machInst.itstateMask != 0) {
214 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
215 }
216
217 return fault;
218 }

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245
246 if (fault == NoFault) {
247 %(postacc_code)s;
248 }
249
250 if (fault == NoFault) {
251 %(op_wb)s;
252 }
253 } else {
254 xc->setPredicate(false);
245 }
246
247 if (fault == NoFault && machInst.itstateMask != 0) {
248 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
249 }
250
251 return fault;
252 }

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274 memAccessFlags, NULL);
275 if (traceData) { traceData->setData(Mem); }
276 }
277
278 // Need to write back any potential address register update
279 if (fault == NoFault) {
280 %(op_wb)s;
281 }
255 }
256
257 if (fault == NoFault && machInst.itstateMask != 0) {
258 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
259 }
260
261 return fault;
262 }

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284 memAccessFlags, NULL);
285 if (traceData) { traceData->setData(Mem); }
286 }
287
288 // Need to write back any potential address register update
289 if (fault == NoFault) {
290 %(op_wb)s;
291 }
292 } else {
293 xc->setPredicate(false);
282 }
283
284 if (fault == NoFault && machInst.itstateMask != 0) {
285 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
286 }
287
288 return fault;
289 }

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311 memAccessFlags, NULL);
312 if (traceData) { traceData->setData(Mem); }
313 }
314
315 // Need to write back any potential address register update
316 if (fault == NoFault) {
317 %(op_wb)s;
318 }
294 }
295
296 if (fault == NoFault && machInst.itstateMask != 0) {
297 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
298 }
299
300 return fault;
301 }

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323 memAccessFlags, NULL);
324 if (traceData) { traceData->setData(Mem); }
325 }
326
327 // Need to write back any potential address register update
328 if (fault == NoFault) {
329 %(op_wb)s;
330 }
331 } else {
332 xc->setPredicate(false);
319 }
320
321 if (fault == NoFault && machInst.itstateMask != 0) {
322 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
323 }
324
325 return fault;
326 }

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337 %(op_rd)s;
338 %(ea_code)s;
339
340 if (%(predicate_test)s)
341 {
342 if (fault == NoFault) {
343 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
344 }
333 }
334
335 if (fault == NoFault && machInst.itstateMask != 0) {
336 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
337 }
338
339 return fault;
340 }

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351 %(op_rd)s;
352 %(ea_code)s;
353
354 if (%(predicate_test)s)
355 {
356 if (fault == NoFault) {
357 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
358 }
345 } else if (fault == NoFault && machInst.itstateMask != 0) {
346 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
359 } else {
360 xc->setPredicate(false);
361 if (fault == NoFault && machInst.itstateMask != 0) {
362 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
363 }
347 }
348
349 return fault;
350 }
351}};
352
353def template LoadCompleteAcc {{
354 Fault %(class_name)s::completeAcc(PacketPtr pkt,

--- 382 unchanged lines hidden --- 		364 }
365
366 return fault;
367 }
368}};
369
370def template LoadCompleteAcc {{
371 Fault %(class_name)s::completeAcc(PacketPtr pkt,

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