mem.isa (7312:03016344f54e) mem.isa (7408:ee6949c5bb5b)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 }
73
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 }
73
74 if (fault == NoFault && machInst.itstateMask != 0) {
75 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
76 }
77
74 return fault;
75 }
76}};
77
78def template SwapInitiateAcc {{
79 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
80 Trace::InstRecord *traceData) const
81 {

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96 memAccessFlags, &memData);
97 }
98
99 if (fault == NoFault) {
100 %(op_wb)s;
101 }
102 }
103
78 return fault;
79 }
80}};
81
82def template SwapInitiateAcc {{
83 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
84 Trace::InstRecord *traceData) const
85 {

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100 memAccessFlags, &memData);
101 }
102
103 if (fault == NoFault) {
104 %(op_wb)s;
105 }
106 }
107
108 if (fault == NoFault && machInst.itstateMask != 0) {
109 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
110 }
111
104 return fault;
105 }
106}};
107
108def template SwapCompleteAcc {{
109 Fault %(class_name)s::completeAcc(PacketPtr pkt,
110 %(CPU_exec_context)s *xc,
111 Trace::InstRecord *traceData) const

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122
123 %(postacc_code)s;
124
125 if (fault == NoFault) {
126 %(op_wb)s;
127 }
128 }
129
112 return fault;
113 }
114}};
115
116def template SwapCompleteAcc {{
117 Fault %(class_name)s::completeAcc(PacketPtr pkt,
118 %(CPU_exec_context)s *xc,
119 Trace::InstRecord *traceData) const

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130
131 %(postacc_code)s;
132
133 if (fault == NoFault) {
134 %(op_wb)s;
135 }
136 }
137
138 if (fault == NoFault && machInst.itstateMask != 0) {
139 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
140 }
141
130 return fault;
131 }
132}};
133
134def template LoadExecute {{
135 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
136 Trace::InstRecord *traceData) const
137 {

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149 %(memacc_code)s;
150 }
151
152 if (fault == NoFault) {
153 %(op_wb)s;
154 }
155 }
156
142 return fault;
143 }
144}};
145
146def template LoadExecute {{
147 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
148 Trace::InstRecord *traceData) const
149 {

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161 %(memacc_code)s;
162 }
163
164 if (fault == NoFault) {
165 %(op_wb)s;
166 }
167 }
168
169 if (fault == NoFault && machInst.itstateMask != 0) {
170 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
171 }
172
157 return fault;
158 }
159}};
160
161def template StoreExecute {{
162 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
163 Trace::InstRecord *traceData) const
164 {

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181 if (traceData) { traceData->setData(Mem); }
182 }
183
184 if (fault == NoFault) {
185 %(op_wb)s;
186 }
187 }
188
173 return fault;
174 }
175}};
176
177def template StoreExecute {{
178 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
179 Trace::InstRecord *traceData) const
180 {

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197 if (traceData) { traceData->setData(Mem); }
198 }
199
200 if (fault == NoFault) {
201 %(op_wb)s;
202 }
203 }
204
205 if (fault == NoFault && machInst.itstateMask != 0) {
206 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
207 }
208
189 return fault;
190 }
191}};
192
193def template StoreExExecute {{
194 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
195 Trace::InstRecord *traceData) const
196 {

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219 %(postacc_code)s;
220 }
221
222 if (fault == NoFault) {
223 %(op_wb)s;
224 }
225 }
226
209 return fault;
210 }
211}};
212
213def template StoreExExecute {{
214 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
215 Trace::InstRecord *traceData) const
216 {

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239 %(postacc_code)s;
240 }
241
242 if (fault == NoFault) {
243 %(op_wb)s;
244 }
245 }
246
247 if (fault == NoFault && machInst.itstateMask != 0) {
248 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
249 }
250
227 return fault;
228 }
229}};
230
231def template StoreExInitiateAcc {{
232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
233 Trace::InstRecord *traceData) const
234 {

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252 }
253
254 // Need to write back any potential address register update
255 if (fault == NoFault) {
256 %(op_wb)s;
257 }
258 }
259
251 return fault;
252 }
253}};
254
255def template StoreExInitiateAcc {{
256 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
257 Trace::InstRecord *traceData) const
258 {

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276 }
277
278 // Need to write back any potential address register update
279 if (fault == NoFault) {
280 %(op_wb)s;
281 }
282 }
283
284 if (fault == NoFault && machInst.itstateMask != 0) {
285 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
286 }
287
260 return fault;
261 }
262}};
263
264def template StoreInitiateAcc {{
265 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
266 Trace::InstRecord *traceData) const
267 {

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285 }
286
287 // Need to write back any potential address register update
288 if (fault == NoFault) {
289 %(op_wb)s;
290 }
291 }
292
288 return fault;
289 }
290}};
291
292def template StoreInitiateAcc {{
293 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
294 Trace::InstRecord *traceData) const
295 {

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313 }
314
315 // Need to write back any potential address register update
316 if (fault == NoFault) {
317 %(op_wb)s;
318 }
319 }
320
321 if (fault == NoFault && machInst.itstateMask != 0) {
322 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
323 }
324
293 return fault;
294 }
295}};
296
297def template LoadInitiateAcc {{
298 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
299 Trace::InstRecord *traceData) const
300 {

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335 %(memacc_code)s;
336 }
337
338 if (fault == NoFault) {
339 %(op_wb)s;
340 }
341 }
342
325 return fault;
326 }
327}};
328
329def template LoadInitiateAcc {{
330 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
331 Trace::InstRecord *traceData) const
332 {

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367 %(memacc_code)s;
368 }
369
370 if (fault == NoFault) {
371 %(op_wb)s;
372 }
373 }
374
375 if (fault == NoFault && machInst.itstateMask != 0) {
376 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
377 }
378
343 return fault;
344 }
345}};
346
347def template StoreCompleteAcc {{
348 Fault %(class_name)s::completeAcc(PacketPtr pkt,
349 %(CPU_exec_context)s *xc,
350 Trace::InstRecord *traceData) const

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356
357 if (%(predicate_test)s)
358 {
359 if (fault == NoFault) {
360 %(op_wb)s;
361 }
362 }
363
379 return fault;
380 }
381}};
382
383def template StoreCompleteAcc {{
384 Fault %(class_name)s::completeAcc(PacketPtr pkt,
385 %(CPU_exec_context)s *xc,
386 Trace::InstRecord *traceData) const

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392
393 if (%(predicate_test)s)
394 {
395 if (fault == NoFault) {
396 %(op_wb)s;
397 }
398 }
399
400 if (fault == NoFault && machInst.itstateMask != 0) {
401 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
402 }
403
364 return fault;
365 }
366}};
367
368def template StoreExCompleteAcc {{
369 Fault %(class_name)s::completeAcc(PacketPtr pkt,
370 %(CPU_exec_context)s *xc,
371 Trace::InstRecord *traceData) const

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380 uint64_t writeResult = pkt->req->getExtraData();
381 %(postacc_code)s;
382
383 if (fault == NoFault) {
384 %(op_wb)s;
385 }
386 }
387
404 return fault;
405 }
406}};
407
408def template StoreExCompleteAcc {{
409 Fault %(class_name)s::completeAcc(PacketPtr pkt,
410 %(CPU_exec_context)s *xc,
411 Trace::InstRecord *traceData) const

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420 uint64_t writeResult = pkt->req->getExtraData();
421 %(postacc_code)s;
422
423 if (fault == NoFault) {
424 %(op_wb)s;
425 }
426 }
427
428 if (fault == NoFault && machInst.itstateMask != 0) {
429 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
430 }
431
388 return fault;
389 }
390}};
391
392def template RfeDeclare {{
393 /**
394 * Static instruction class for "%(mnemonic)s".
395 */

--- 295 unchanged lines hidden --- 		432 return fault;
433 }
434}};
435
436def template RfeDeclare {{
437 /**
438 * Static instruction class for "%(mnemonic)s".
439 */

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