mem.isa (7120:d630089169f3) mem.isa (7205:e3dfcdf19561)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template SwapExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;
52 uint64_t memData = 0;
53 %(op_rd)s;
54 %(ea_code)s;
55
56 if (%(predicate_test)s)
57 {
58 %(preacc_code)s;
59
60 if (fault == NoFault) {
61 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
62 EA, memAccessFlags, &memData);
63 }
64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 }
73
74 return fault;
75 }
76}};
77
78def template SwapInitiateAcc {{
79 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
80 Trace::InstRecord *traceData) const
81 {
82 Addr EA;
83 Fault fault = NoFault;
84
85 %(op_decl)s;
86 uint64_t memData = 0;
87 %(op_rd)s;
88 %(ea_code)s;
89
90 if (%(predicate_test)s)
91 {
92 %(preacc_code)s;
93
94 if (fault == NoFault) {
95 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
96 memAccessFlags, &memData);
97 }
98
99 if (fault == NoFault) {
100 %(op_wb)s;
101 }
102 }
103
104 return fault;
105 }
106}};
107
108def template SwapCompleteAcc {{
109 Fault %(class_name)s::completeAcc(PacketPtr pkt,
110 %(CPU_exec_context)s *xc,
111 Trace::InstRecord *traceData) const
112 {
113 Fault fault = NoFault;
114
115 %(op_decl)s;
116 %(op_rd)s;
117
118 if (%(predicate_test)s)
119 {
120 // ARM instructions will not have a pkt if the predicate is false
121 uint64_t memData = pkt->get<typeof(Mem)>();
122
123 %(postacc_code)s;
124
125 if (fault == NoFault) {
126 %(op_wb)s;
127 }
128 }
129
130 return fault;
131 }
132}};
133
44def template LoadExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;

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199 %(op_wb)s;
200 }
201 }
202
203 return fault;
204 }
205}};
206
134def template LoadExecute {{
135 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
136 Trace::InstRecord *traceData) const
137 {
138 Addr EA;
139 Fault fault = NoFault;
140
141 %(op_decl)s;

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289 %(op_wb)s;
290 }
291 }
292
293 return fault;
294 }
295}};
296
297def template SwapDeclare {{
298 /**
299 * Static instruction class for "%(mnemonic)s".
300 */
301 class %(class_name)s : public %(base_class)s
302 {
303 public:
304
305 /// Constructor.
306 %(class_name)s(ExtMachInst machInst,
307 uint32_t _dest, uint32_t _op1, uint32_t _base);
308
309 %(BasicExecDeclare)s
310
311 %(InitiateAccDeclare)s
312
313 %(CompleteAccDeclare)s
314 };
315}};
316
207def template LoadStoreImmDeclare {{
208 /**
209 * Static instruction class for "%(mnemonic)s".
210 */
211 class %(class_name)s : public %(base_class)s
212 {
213 public:
214

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249def template InitiateAccDeclare {{
250 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
251}};
252
253def template CompleteAccDeclare {{
254 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
255}};
256
317def template LoadStoreImmDeclare {{
318 /**
319 * Static instruction class for "%(mnemonic)s".
320 */
321 class %(class_name)s : public %(base_class)s
322 {
323 public:
324

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359def template InitiateAccDeclare {{
360 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
361}};
362
363def template CompleteAccDeclare {{
364 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
365}};
366
367def template SwapConstructor {{
368 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
369 uint32_t _dest, uint32_t _op1, uint32_t _base)
370 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
371 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
372 {
373 %(constructor)s;
374 }
375}};
376
257def template LoadStoreImmConstructor {{
258 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
259 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
260 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
261 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
262 {
263 %(constructor)s;
264 }

--- 14 unchanged lines hidden --- 		377def template LoadStoreImmConstructor {{
378 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
379 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
380 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
381 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
382 {
383 %(constructor)s;
384 }

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