mem.isa (7119:5ad962dec52f) mem.isa (7120:d630089169f3)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright

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51 %(op_wb)s;
52 }
53 }
54
55 return fault;
56 }
57}};
58
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright

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63 %(op_wb)s;
64 }
65 }
66
67 return fault;
68 }
69}};
70
71def template StoreExecute {{
72 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
73 Trace::InstRecord *traceData) const
74 {
75 Addr EA;
76 Fault fault = NoFault;
77
78 %(op_decl)s;
79 %(op_rd)s;
80 %(ea_code)s;
81
82 if (%(predicate_test)s)
83 {
84 if (fault == NoFault) {
85 %(memacc_code)s;
86 }
87
88 if (fault == NoFault) {
89 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
90 memAccessFlags, NULL);
91 if (traceData) { traceData->setData(Mem); }
92 }
93
94 if (fault == NoFault) {
95 %(op_wb)s;
96 }
97 }
98
99 return fault;
100 }
101}};
102
103def template StoreInitiateAcc {{
104 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
105 Trace::InstRecord *traceData) const
106 {
107 Addr EA;
108 Fault fault = NoFault;
109
110 %(op_decl)s;
111 %(op_rd)s;
112 %(ea_code)s;
113
114 if (%(predicate_test)s)
115 {
116 if (fault == NoFault) {
117 %(memacc_code)s;
118 }
119
120 if (fault == NoFault) {
121 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
122 memAccessFlags, NULL);
123 if (traceData) { traceData->setData(Mem); }
124 }
125
126 // Need to write back any potential address register update
127 if (fault == NoFault) {
128 %(op_wb)s;
129 }
130 }
131
132 return fault;
133 }
134}};
135
59def template LoadInitiateAcc {{
60 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
61 Trace::InstRecord *traceData) const
62 {
63 Addr EA;
64 Fault fault = NoFault;
65
66 %(op_src_decl)s;

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101 %(op_wb)s;
102 }
103 }
104
105 return fault;
106 }
107}};
108
136def template LoadInitiateAcc {{
137 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
138 Trace::InstRecord *traceData) const
139 {
140 Addr EA;
141 Fault fault = NoFault;
142
143 %(op_src_decl)s;

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178 %(op_wb)s;
179 }
180 }
181
182 return fault;
183 }
184}};
185
186def template StoreCompleteAcc {{
187 Fault %(class_name)s::completeAcc(PacketPtr pkt,
188 %(CPU_exec_context)s *xc,
189 Trace::InstRecord *traceData) const
190 {
191 Fault fault = NoFault;
192
193 %(op_decl)s;
194 %(op_rd)s;
195
196 if (%(predicate_test)s)
197 {
198 if (fault == NoFault) {
199 %(op_wb)s;
200 }
201 }
202
203 return fault;
204 }
205}};
206
109def template LoadStoreImmDeclare {{
110 /**
111 * Static instruction class for "%(mnemonic)s".
112 */
113 class %(class_name)s : public %(base_class)s
114 {
115 public:
116

--- 64 unchanged lines hidden --- 		207def template LoadStoreImmDeclare {{
208 /**
209 * Static instruction class for "%(mnemonic)s".
210 */
211 class %(class_name)s : public %(base_class)s
212 {
213 public:
214

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