mem.isa (11303:f694764d656d) | mem.isa (12110:c24ee249b8ba) |
---|---|
1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2010, 2012, 2014 ARM Limited | 3// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited |
4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 1133 unchanged lines hidden (view full) --- 1145 conditional = true; 1146 for (int x = 0; x < _numDestRegs; x++) { 1147 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1148 } 1149 } 1150#if %(use_uops)d 1151 assert(numMicroops >= 2); 1152 uops = new StaticInstPtr[numMicroops]; | 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated --- 1133 unchanged lines hidden (view full) --- 1145 conditional = true; 1146 for (int x = 0; x < _numDestRegs; x++) { 1147 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1148 } 1149 } 1150#if %(use_uops)d 1151 assert(numMicroops >= 2); 1152 uops = new StaticInstPtr[numMicroops]; |
1153 if (_dest == INTREG_PC && !isFloating()) { | 1153 if (_dest == INTREG_PC && !isFloating() && !isVector()) { |
1154 IntRegIndex wbIndexReg = index; 1155 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1156 _shiftAmt, _shiftType, _index); 1157 uops[0]->setDelayedCommit(); 1158 uops[0]->setFirstMicroop(); 1159 uops[1] = new %(wb_decl)s; 1160 uops[1]->setDelayedCommit(); 1161 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); --- 20 unchanged lines hidden (view full) --- 1182 _shiftAmt, _shiftType, _index); 1183 uops[0]->setDelayedCommit(); 1184 uops[0]->setFirstMicroop(); 1185 uops[1] = new %(wb_decl)s; 1186 uops[1]->setLastMicroop(); 1187 1188 } 1189#else | 1154 IntRegIndex wbIndexReg = index; 1155 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1156 _shiftAmt, _shiftType, _index); 1157 uops[0]->setDelayedCommit(); 1158 uops[0]->setFirstMicroop(); 1159 uops[1] = new %(wb_decl)s; 1160 uops[1]->setDelayedCommit(); 1161 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); --- 20 unchanged lines hidden (view full) --- 1182 _shiftAmt, _shiftType, _index); 1183 uops[0]->setDelayedCommit(); 1184 uops[0]->setFirstMicroop(); 1185 uops[1] = new %(wb_decl)s; 1186 uops[1]->setLastMicroop(); 1187 1188 } 1189#else |
1190 if (_dest == INTREG_PC && !isFloating()) { | 1190 if (_dest == INTREG_PC && !isFloating() && !isVector()) { |
1191 flags[IsControl] = true; 1192 flags[IsIndirectControl] = true; 1193 if (conditional) 1194 flags[IsCondControl] = true; 1195 else 1196 flags[IsUncondControl] = true; 1197 } 1198#endif --- 12 unchanged lines hidden (view full) --- 1211 conditional = true; 1212 for (int x = 0; x < _numDestRegs; x++) { 1213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1214 } 1215 } 1216#if %(use_uops)d 1217 assert(numMicroops >= 2); 1218 uops = new StaticInstPtr[numMicroops]; | 1191 flags[IsControl] = true; 1192 flags[IsIndirectControl] = true; 1193 if (conditional) 1194 flags[IsCondControl] = true; 1195 else 1196 flags[IsUncondControl] = true; 1197 } 1198#endif --- 12 unchanged lines hidden (view full) --- 1211 conditional = true; 1212 for (int x = 0; x < _numDestRegs; x++) { 1213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1214 } 1215 } 1216#if %(use_uops)d 1217 assert(numMicroops >= 2); 1218 uops = new StaticInstPtr[numMicroops]; |
1219 if (_dest == INTREG_PC && !isFloating()) { | 1219 if (_dest == INTREG_PC && !isFloating() && !isVector()) { |
1220 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1221 _imm); 1222 uops[0]->setDelayedCommit(); 1223 uops[0]->setFirstMicroop(); 1224 uops[1] = new %(wb_decl)s; 1225 uops[1]->setDelayedCommit(); 1226 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1227 uops[2]->setFlag(StaticInst::IsControl); --- 17 unchanged lines hidden (view full) --- 1245 } else { 1246 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 1247 uops[0]->setDelayedCommit(); 1248 uops[0]->setFirstMicroop(); 1249 uops[1] = new %(wb_decl)s; 1250 uops[1]->setLastMicroop(); 1251 } 1252#else | 1220 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1221 _imm); 1222 uops[0]->setDelayedCommit(); 1223 uops[0]->setFirstMicroop(); 1224 uops[1] = new %(wb_decl)s; 1225 uops[1]->setDelayedCommit(); 1226 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1227 uops[2]->setFlag(StaticInst::IsControl); --- 17 unchanged lines hidden (view full) --- 1245 } else { 1246 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 1247 uops[0]->setDelayedCommit(); 1248 uops[0]->setFirstMicroop(); 1249 uops[1] = new %(wb_decl)s; 1250 uops[1]->setLastMicroop(); 1251 } 1252#else |
1253 if (_dest == INTREG_PC && !isFloating()) { | 1253 if (_dest == INTREG_PC && !isFloating() && !isVector()) { |
1254 flags[IsControl] = true; 1255 flags[IsIndirectControl] = true; 1256 if (conditional) 1257 flags[IsCondControl] = true; 1258 else 1259 flags[IsUncondControl] = true; 1260 } 1261#endif 1262 } 1263}}; 1264 | 1254 flags[IsControl] = true; 1255 flags[IsIndirectControl] = true; 1256 if (conditional) 1257 flags[IsCondControl] = true; 1258 else 1259 flags[IsUncondControl] = true; 1260 } 1261#endif 1262 } 1263}}; 1264 |