mem.isa (10037:5cac77888310) mem.isa (10184:bbfa3152bdea)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010, 2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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855 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
856}};
857
858def template CompleteAccDeclare {{
859 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
860}};
861
862def template RfeConstructor {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010, 2012 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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855 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
856}};
857
858def template CompleteAccDeclare {{
859 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
860}};
861
862def template RfeConstructor {{
863 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
863 %(class_name)s::%(class_name)s(ExtMachInst machInst,
864 uint32_t _base, int _mode, bool _wb)
865 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
866 (IntRegIndex)_base, (AddrMode)_mode, _wb)
867 {
868 %(constructor)s;
869 if (!(condCode == COND_AL || condCode == COND_UC)) {
870 for (int x = 0; x < _numDestRegs; x++) {
871 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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884 uops[++uopIdx] = new %(pc_decl)s;
885#endif
886 uops[uopIdx]->setLastMicroop();
887#endif
888 }
889}};
890
891def template SrsConstructor {{
864 uint32_t _base, int _mode, bool _wb)
865 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
866 (IntRegIndex)_base, (AddrMode)_mode, _wb)
867 {
868 %(constructor)s;
869 if (!(condCode == COND_AL || condCode == COND_UC)) {
870 for (int x = 0; x < _numDestRegs; x++) {
871 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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884 uops[++uopIdx] = new %(pc_decl)s;
885#endif
886 uops[uopIdx]->setLastMicroop();
887#endif
888 }
889}};
890
891def template SrsConstructor {{
892 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
892 %(class_name)s::%(class_name)s(ExtMachInst machInst,
893 uint32_t _regMode, int _mode, bool _wb)
894 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
895 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
896 {
897 %(constructor)s;
898 if (!(condCode == COND_AL || condCode == COND_UC)) {
899 for (int x = 0; x < _numDestRegs; x++) {
900 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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907 uops[0]->setDelayedCommit();
908 uops[1] = new %(wb_decl)s;
909 uops[1]->setLastMicroop();
910#endif
911 }
912}};
913
914def template SwapConstructor {{
893 uint32_t _regMode, int _mode, bool _wb)
894 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
895 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
896 {
897 %(constructor)s;
898 if (!(condCode == COND_AL || condCode == COND_UC)) {
899 for (int x = 0; x < _numDestRegs; x++) {
900 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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907 uops[0]->setDelayedCommit();
908 uops[1] = new %(wb_decl)s;
909 uops[1]->setLastMicroop();
910#endif
911 }
912}};
913
914def template SwapConstructor {{
915 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
915 %(class_name)s::%(class_name)s(ExtMachInst machInst,
916 uint32_t _dest, uint32_t _op1, uint32_t _base)
917 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
918 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
919 {
920 %(constructor)s;
921 if (!(condCode == COND_AL || condCode == COND_UC)) {
922 for (int x = 0; x < _numDestRegs; x++) {
923 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
924 }
925 }
926 }
927}};
928
929def template LoadStoreDImmConstructor {{
916 uint32_t _dest, uint32_t _op1, uint32_t _base)
917 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
918 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
919 {
920 %(constructor)s;
921 if (!(condCode == COND_AL || condCode == COND_UC)) {
922 for (int x = 0; x < _numDestRegs; x++) {
923 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
924 }
925 }
926 }
927}};
928
929def template LoadStoreDImmConstructor {{
930 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
930 %(class_name)s::%(class_name)s(ExtMachInst machInst,
931 uint32_t _dest, uint32_t _dest2,
932 uint32_t _base, bool _add, int32_t _imm)
933 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
934 (IntRegIndex)_dest, (IntRegIndex)_dest2,
935 (IntRegIndex)_base, _add, _imm)
936 {
937 %(constructor)s;
938 if (!(condCode == COND_AL || condCode == COND_UC)) {

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947 uops[0]->setDelayedCommit();
948 uops[1] = new %(wb_decl)s;
949 uops[1]->setLastMicroop();
950#endif
951 }
952}};
953
954def template StoreExDImmConstructor {{
931 uint32_t _dest, uint32_t _dest2,
932 uint32_t _base, bool _add, int32_t _imm)
933 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
934 (IntRegIndex)_dest, (IntRegIndex)_dest2,
935 (IntRegIndex)_base, _add, _imm)
936 {
937 %(constructor)s;
938 if (!(condCode == COND_AL || condCode == COND_UC)) {

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947 uops[0]->setDelayedCommit();
948 uops[1] = new %(wb_decl)s;
949 uops[1]->setLastMicroop();
950#endif
951 }
952}};
953
954def template StoreExDImmConstructor {{
955 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
955 %(class_name)s::%(class_name)s(ExtMachInst machInst,
956 uint32_t _result, uint32_t _dest, uint32_t _dest2,
957 uint32_t _base, bool _add, int32_t _imm)
958 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
959 (IntRegIndex)_result,
960 (IntRegIndex)_dest, (IntRegIndex)_dest2,
961 (IntRegIndex)_base, _add, _imm)
962 {
963 %(constructor)s;

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974 uops[0]->setDelayedCommit();
975 uops[1] = new %(wb_decl)s;
976 uops[1]->setLastMicroop();
977#endif
978 }
979}};
980
981def template LoadStoreImmConstructor {{
956 uint32_t _result, uint32_t _dest, uint32_t _dest2,
957 uint32_t _base, bool _add, int32_t _imm)
958 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
959 (IntRegIndex)_result,
960 (IntRegIndex)_dest, (IntRegIndex)_dest2,
961 (IntRegIndex)_base, _add, _imm)
962 {
963 %(constructor)s;

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974 uops[0]->setDelayedCommit();
975 uops[1] = new %(wb_decl)s;
976 uops[1]->setLastMicroop();
977#endif
978 }
979}};
980
981def template LoadStoreImmConstructor {{
982 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
982 %(class_name)s::%(class_name)s(ExtMachInst machInst,
983 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
984 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
985 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
986 {
987 %(constructor)s;
988 if (!(condCode == COND_AL || condCode == COND_UC)) {
989 for (int x = 0; x < _numDestRegs; x++) {
990 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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997 uops[0]->setDelayedCommit();
998 uops[1] = new %(wb_decl)s;
999 uops[1]->setLastMicroop();
1000#endif
1001 }
1002}};
1003
1004def template StoreExImmConstructor {{
983 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
984 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
985 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
986 {
987 %(constructor)s;
988 if (!(condCode == COND_AL || condCode == COND_UC)) {
989 for (int x = 0; x < _numDestRegs; x++) {
990 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];

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997 uops[0]->setDelayedCommit();
998 uops[1] = new %(wb_decl)s;
999 uops[1]->setLastMicroop();
1000#endif
1001 }
1002}};
1003
1004def template StoreExImmConstructor {{
1005 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1005 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1006 uint32_t _result, uint32_t _dest, uint32_t _base,
1007 bool _add, int32_t _imm)
1008 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1009 (IntRegIndex)_result, (IntRegIndex)_dest,
1010 (IntRegIndex)_base, _add, _imm)
1011 {
1012 %(constructor)s;
1013 if (!(condCode == COND_AL || condCode == COND_UC)) {

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1023 uops[0]->setDelayedCommit();
1024 uops[1] = new %(wb_decl)s;
1025 uops[1]->setLastMicroop();
1026#endif
1027 }
1028}};
1029
1030def template StoreDRegConstructor {{
1006 uint32_t _result, uint32_t _dest, uint32_t _base,
1007 bool _add, int32_t _imm)
1008 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1009 (IntRegIndex)_result, (IntRegIndex)_dest,
1010 (IntRegIndex)_base, _add, _imm)
1011 {
1012 %(constructor)s;
1013 if (!(condCode == COND_AL || condCode == COND_UC)) {

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1023 uops[0]->setDelayedCommit();
1024 uops[1] = new %(wb_decl)s;
1025 uops[1]->setLastMicroop();
1026#endif
1027 }
1028}};
1029
1030def template StoreDRegConstructor {{
1031 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1031 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1032 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1033 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1034 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1035 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1036 (IntRegIndex)_base, _add,
1037 _shiftAmt, (ArmShiftType)_shiftType,
1038 (IntRegIndex)_index)
1039 {

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1051 uops[0]->setDelayedCommit();
1052 uops[1] = new %(wb_decl)s;
1053 uops[1]->setLastMicroop();
1054#endif
1055 }
1056}};
1057
1058def template StoreRegConstructor {{
1032 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1033 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1034 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1035 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1036 (IntRegIndex)_base, _add,
1037 _shiftAmt, (ArmShiftType)_shiftType,
1038 (IntRegIndex)_index)
1039 {

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1051 uops[0]->setDelayedCommit();
1052 uops[1] = new %(wb_decl)s;
1053 uops[1]->setLastMicroop();
1054#endif
1055 }
1056}};
1057
1058def template StoreRegConstructor {{
1059 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1059 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1060 uint32_t _dest, uint32_t _base, bool _add,
1061 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1062 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1063 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1064 _shiftAmt, (ArmShiftType)_shiftType,
1065 (IntRegIndex)_index)
1066 {
1067 %(constructor)s;

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1078 uops[0]->setDelayedCommit();
1079 uops[1] = new %(wb_decl)s;
1080 uops[1]->setLastMicroop();
1081#endif
1082 }
1083}};
1084
1085def template LoadDRegConstructor {{
1060 uint32_t _dest, uint32_t _base, bool _add,
1061 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1062 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1063 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1064 _shiftAmt, (ArmShiftType)_shiftType,
1065 (IntRegIndex)_index)
1066 {
1067 %(constructor)s;

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1078 uops[0]->setDelayedCommit();
1079 uops[1] = new %(wb_decl)s;
1080 uops[1]->setLastMicroop();
1081#endif
1082 }
1083}};
1084
1085def template LoadDRegConstructor {{
1086 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1086 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1087 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1088 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1089 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1090 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1091 (IntRegIndex)_base, _add,
1092 _shiftAmt, (ArmShiftType)_shiftType,
1093 (IntRegIndex)_index)
1094 {

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1118 uops[1] = new %(wb_decl)s;
1119 uops[1]->setLastMicroop();
1120 }
1121#endif
1122 }
1123}};
1124
1125def template LoadRegConstructor {{
1087 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1088 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1089 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1090 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1091 (IntRegIndex)_base, _add,
1092 _shiftAmt, (ArmShiftType)_shiftType,
1093 (IntRegIndex)_index)
1094 {

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1118 uops[1] = new %(wb_decl)s;
1119 uops[1]->setLastMicroop();
1120 }
1121#endif
1122 }
1123}};
1124
1125def template LoadRegConstructor {{
1126 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1126 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1127 uint32_t _dest, uint32_t _base, bool _add,
1128 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1129 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1130 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1131 _shiftAmt, (ArmShiftType)_shiftType,
1132 (IntRegIndex)_index)
1133 {
1134 %(constructor)s;

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1184 else
1185 flags[IsUncondControl] = true;
1186 }
1187#endif
1188 }
1189}};
1190
1191def template LoadImmConstructor {{
1127 uint32_t _dest, uint32_t _base, bool _add,
1128 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1129 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1130 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1131 _shiftAmt, (ArmShiftType)_shiftType,
1132 (IntRegIndex)_index)
1133 {
1134 %(constructor)s;

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1184 else
1185 flags[IsUncondControl] = true;
1186 }
1187#endif
1188 }
1189}};
1190
1191def template LoadImmConstructor {{
1192 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1192 %(class_name)s::%(class_name)s(ExtMachInst machInst,
1193 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1194 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1195 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1196 {
1197 %(constructor)s;
1198 bool conditional M5_VAR_USED = false;
1199 if (!(condCode == COND_AL || condCode == COND_UC)) {
1200 conditional = true;

--- 42 unchanged lines hidden --- 		1193 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1194 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1195 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1196 {
1197 %(constructor)s;
1198 bool conditional M5_VAR_USED = false;
1199 if (!(condCode == COND_AL || condCode == COND_UC)) {
1200 conditional = true;

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