1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 1098 unchanged lines hidden (view full) --- 1107 uint32_t _dest, uint32_t _base, bool _add, 1108 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 1109 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1110 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 1111 _shiftAmt, (ArmShiftType)_shiftType, 1112 (IntRegIndex)_index) 1113 { 1114 %(constructor)s; |
1115 bool conditional M5_VAR_USED = false; |
1116 if (!(condCode == COND_AL || condCode == COND_UC)) { 1117 conditional = true; 1118 for (int x = 0; x < _numDestRegs; x++) { 1119 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1120 } 1121 } 1122#if %(use_uops)d 1123 assert(numMicroops >= 2); --- 37 unchanged lines hidden (view full) --- 1161 1162def template LoadImmConstructor {{ 1163 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1164 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1166 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1167 { 1168 %(constructor)s; |
1169 bool conditional M5_VAR_USED = false; |
1170 if (!(condCode == COND_AL || condCode == COND_UC)) { 1171 conditional = true; 1172 for (int x = 0; x < _numDestRegs; x++) { 1173 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1174 } 1175 } 1176#if %(use_uops)d 1177 assert(numMicroops >= 2); --- 27 unchanged lines hidden --- |