1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 903 unchanged lines hidden (view full) --- 912 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 913 (IntRegIndex)_base, (AddrMode)_mode, _wb) 914 { 915 %(constructor)s; 916#if %(use_uops)d 917 assert(numMicroops >= 2); 918 uops = new StaticInstPtr[numMicroops]; 919 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb); |
920 uops[0]->setDelayedCommit(); |
921 uops[1] = new %(wb_decl)s; 922 uops[1]->setLastMicroop(); 923#endif 924 } 925}}; 926 927def template SrsConstructor {{ 928 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 929 uint32_t _regMode, int _mode, bool _wb) 930 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 931 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 932 { 933 %(constructor)s; 934#if %(use_uops)d 935 assert(numMicroops >= 2); 936 uops = new StaticInstPtr[numMicroops]; 937 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); |
938 uops[0]->setDelayedCommit(); |
939 uops[1] = new %(wb_decl)s; 940 uops[1]->setLastMicroop(); 941#endif 942 } 943}}; 944 945def template SwapConstructor {{ 946 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 13 unchanged lines hidden (view full) --- 960 (IntRegIndex)_dest, (IntRegIndex)_dest2, 961 (IntRegIndex)_base, _add, _imm) 962 { 963 %(constructor)s; 964#if %(use_uops)d 965 assert(numMicroops >= 2); 966 uops = new StaticInstPtr[numMicroops]; 967 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); |
968 uops[0]->setDelayedCommit(); |
969 uops[1] = new %(wb_decl)s; 970 uops[1]->setLastMicroop(); 971#endif 972 } 973}}; 974 975def template StoreExDImmConstructor {{ 976 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 5 unchanged lines hidden (view full) --- 982 (IntRegIndex)_base, _add, _imm) 983 { 984 %(constructor)s; 985#if %(use_uops)d 986 assert(numMicroops >= 2); 987 uops = new StaticInstPtr[numMicroops]; 988 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 989 _base, _add, _imm); |
990 uops[0]->setDelayedCommit(); |
991 uops[1] = new %(wb_decl)s; 992 uops[1]->setLastMicroop(); 993#endif 994 } 995}}; 996 997def template LoadStoreImmConstructor {{ 998 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 999 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1001 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 1002 { 1003 %(constructor)s; 1004#if %(use_uops)d 1005 assert(numMicroops >= 2); 1006 uops = new StaticInstPtr[numMicroops]; 1007 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); |
1008 uops[0]->setDelayedCommit(); |
1009 uops[1] = new %(wb_decl)s; 1010 uops[1]->setLastMicroop(); 1011#endif 1012 } 1013}}; 1014 1015def template StoreExImmConstructor {{ 1016 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 4 unchanged lines hidden (view full) --- 1021 (IntRegIndex)_base, _add, _imm) 1022 { 1023 %(constructor)s; 1024#if %(use_uops)d 1025 assert(numMicroops >= 2); 1026 uops = new StaticInstPtr[numMicroops]; 1027 uops[0] = new %(acc_name)s(machInst, _result, _dest, 1028 _base, _add, _imm); |
1029 uops[0]->setDelayedCommit(); |
1030 uops[1] = new %(wb_decl)s; 1031 uops[1]->setLastMicroop(); 1032#endif 1033 } 1034}}; 1035 1036def template StoreDRegConstructor {{ 1037 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 6 unchanged lines hidden (view full) --- 1044 (IntRegIndex)_index) 1045 { 1046 %(constructor)s; 1047#if %(use_uops)d 1048 assert(numMicroops >= 2); 1049 uops = new StaticInstPtr[numMicroops]; 1050 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 1051 _shiftAmt, _shiftType, _index); |
1052 uops[0]->setDelayedCommit(); |
1053 uops[1] = new %(wb_decl)s; 1054 uops[1]->setLastMicroop(); 1055#endif 1056 } 1057}}; 1058 1059def template StoreRegConstructor {{ 1060 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 5 unchanged lines hidden (view full) --- 1066 (IntRegIndex)_index) 1067 { 1068 %(constructor)s; 1069#if %(use_uops)d 1070 assert(numMicroops >= 2); 1071 uops = new StaticInstPtr[numMicroops]; 1072 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 1073 _shiftAmt, _shiftType, _index); |
1074 uops[0]->setDelayedCommit(); |
1075 uops[1] = new %(wb_decl)s; 1076 uops[1]->setLastMicroop(); 1077#endif 1078 } 1079}}; 1080 1081def template LoadDRegConstructor {{ 1082 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, --- 7 unchanged lines hidden (view full) --- 1090 { 1091 %(constructor)s; 1092#if %(use_uops)d 1093 assert(numMicroops >= 2); 1094 uops = new StaticInstPtr[numMicroops]; 1095 if ((_dest == _index) || (_dest2 == _index)) { 1096 IntRegIndex wbIndexReg = INTREG_UREG0; 1097 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); |
1098 uops[0]->setDelayedCommit(); |
1099 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 1100 _shiftAmt, _shiftType, _index); |
1101 uops[1]->setDelayedCommit(); |
1102 uops[2] = new %(wb_decl)s; 1103 uops[2]->setLastMicroop(); 1104 } else { 1105 IntRegIndex wbIndexReg = index; 1106 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 1107 _shiftAmt, _shiftType, _index); |
1108 uops[0]->setDelayedCommit(); |
1109 uops[1] = new %(wb_decl)s; 1110 uops[1]->setLastMicroop(); 1111 } 1112#endif 1113 } 1114}}; 1115 1116def template LoadRegConstructor {{ --- 8 unchanged lines hidden (view full) --- 1125 %(constructor)s; 1126#if %(use_uops)d 1127 assert(numMicroops >= 2); 1128 uops = new StaticInstPtr[numMicroops]; 1129 if (_dest == INTREG_PC) { 1130 IntRegIndex wbIndexReg = index; 1131 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1132 _shiftAmt, _shiftType, _index); |
1133 uops[0]->setDelayedCommit(); |
1134 uops[1] = new %(wb_decl)s; |
1135 uops[1]->setDelayedCommit(); |
1136 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1137 uops[2]->setLastMicroop(); 1138 } else if(_dest == _index) { 1139 IntRegIndex wbIndexReg = INTREG_UREG0; 1140 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); |
1141 uops[0]->setDelayedCommit(); |
1142 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 1143 _shiftAmt, _shiftType, _index); |
1144 uops[1]->setDelayedCommit(); |
1145 uops[2] = new %(wb_decl)s; 1146 uops[2]->setLastMicroop(); 1147 } else { 1148 IntRegIndex wbIndexReg = index; 1149 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 1150 _shiftAmt, _shiftType, _index); |
1151 uops[0]->setDelayedCommit(); |
1152 uops[1] = new %(wb_decl)s; 1153 uops[1]->setLastMicroop(); 1154 1155 } 1156#endif 1157 } 1158}}; 1159 --- 5 unchanged lines hidden (view full) --- 1165 { 1166 %(constructor)s; 1167#if %(use_uops)d 1168 assert(numMicroops >= 2); 1169 uops = new StaticInstPtr[numMicroops]; 1170 if (_dest == INTREG_PC) { 1171 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 1172 _imm); |
1173 uops[0]->setDelayedCommit(); |
1174 uops[1] = new %(wb_decl)s; |
1175 uops[1]->setDelayedCommit(); |
1176 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 1177 uops[2]->setLastMicroop(); 1178 } else { 1179 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); |
1180 uops[0]->setDelayedCommit(); |
1181 uops[1] = new %(wb_decl)s; 1182 uops[1]->setLastMicroop(); 1183 } 1184#endif 1185 } 1186}}; 1187 |