1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 166 unchanged lines hidden (view full) --- 175 if (fault == NoFault && machInst.itstateMask != 0) { 176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 177 } 178 179 return fault; 180 } 181}}; 182 |
183def template NeonLoadExecute {{ 184 template <class Element> 185 Fault %(class_name)s<Element>::execute( 186 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 187 { 188 Addr EA; 189 Fault fault = NoFault; 190 191 %(op_decl)s; 192 %(mem_decl)s; 193 %(op_rd)s; 194 %(ea_code)s; 195 196 MemUnion memUnion; 197 uint8_t *dataPtr = memUnion.bytes; 198 199 if (%(predicate_test)s) 200 { 201 if (fault == NoFault) { 202 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags); 203 %(memacc_code)s; 204 } 205 206 if (fault == NoFault) { 207 %(op_wb)s; 208 } 209 } 210 211 if (fault == NoFault && machInst.itstateMask != 0) { 212 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 213 } 214 215 return fault; 216 } 217}}; 218 |
219def template StoreExecute {{ 220 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 221 Trace::InstRecord *traceData) const 222 { 223 Addr EA; 224 Fault fault = NoFault; 225 226 %(op_decl)s; --- 21 unchanged lines hidden (view full) --- 248 if (fault == NoFault && machInst.itstateMask != 0) { 249 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 250 } 251 252 return fault; 253 } 254}}; 255 |
256def template NeonStoreExecute {{ 257 template <class Element> 258 Fault %(class_name)s<Element>::execute( 259 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 260 { 261 Addr EA; 262 Fault fault = NoFault; 263 264 %(op_decl)s; 265 %(mem_decl)s; 266 %(op_rd)s; 267 %(ea_code)s; 268 269 MemUnion memUnion; 270 uint8_t *dataPtr = memUnion.bytes; 271 272 if (%(predicate_test)s) 273 { 274 if (fault == NoFault) { 275 %(memacc_code)s; 276 } 277 278 if (fault == NoFault) { 279 fault = xc->writeBytes(dataPtr, %(size)d, EA, 280 memAccessFlags, NULL); 281 } 282 283 if (fault == NoFault) { 284 %(op_wb)s; 285 } 286 } 287 288 if (fault == NoFault && machInst.itstateMask != 0) { 289 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 290 } 291 292 return fault; 293 } 294}}; 295 |
296def template StoreExExecute {{ 297 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 298 Trace::InstRecord *traceData) const 299 { 300 Addr EA; 301 Fault fault = NoFault; 302 303 %(op_decl)s; --- 103 unchanged lines hidden (view full) --- 407 if (fault == NoFault && machInst.itstateMask != 0) { 408 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 409 } 410 411 return fault; 412 } 413}}; 414 |
415def template NeonStoreInitiateAcc {{ 416 template <class Element> 417 Fault %(class_name)s<Element>::initiateAcc( 418 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 419 { 420 Addr EA; 421 Fault fault = NoFault; 422 423 %(op_decl)s; 424 %(mem_decl)s; 425 %(op_rd)s; 426 %(ea_code)s; 427 428 if (%(predicate_test)s) 429 { 430 MemUnion memUnion; 431 if (fault == NoFault) { 432 %(memacc_code)s; 433 } 434 435 if (fault == NoFault) { 436 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 437 memAccessFlags, NULL); 438 } 439 440 // Need to write back any potential address register update 441 if (fault == NoFault) { 442 %(op_wb)s; 443 } 444 } 445 446 if (fault == NoFault && machInst.itstateMask != 0) { 447 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 448 } 449 450 return fault; 451 } 452}}; 453 |
454def template LoadInitiateAcc {{ 455 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 456 Trace::InstRecord *traceData) const 457 { 458 Addr EA; 459 Fault fault = NoFault; 460 461 %(op_src_decl)s; --- 11 unchanged lines hidden (view full) --- 473 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 474 } 475 } 476 477 return fault; 478 } 479}}; 480 |
481def template NeonLoadInitiateAcc {{ 482 template <class Element> 483 Fault %(class_name)s<Element>::initiateAcc( 484 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 485 { 486 Addr EA; 487 Fault fault = NoFault; 488 489 %(op_src_decl)s; 490 %(op_rd)s; 491 %(ea_code)s; 492 493 if (%(predicate_test)s) 494 { 495 if (fault == NoFault) { 496 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 497 } 498 } else if (fault == NoFault && machInst.itstateMask != 0) { 499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 500 } 501 502 return fault; 503 } 504}}; 505 |
506def template LoadCompleteAcc {{ 507 Fault %(class_name)s::completeAcc(PacketPtr pkt, 508 %(CPU_exec_context)s *xc, 509 Trace::InstRecord *traceData) const 510 { 511 Fault fault = NoFault; 512 513 %(op_decl)s; --- 16 unchanged lines hidden (view full) --- 530 if (fault == NoFault && machInst.itstateMask != 0) { 531 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 532 } 533 534 return fault; 535 } 536}}; 537 |
538def template NeonLoadCompleteAcc {{ 539 template <class Element> 540 Fault %(class_name)s<Element>::completeAcc( 541 PacketPtr pkt, %(CPU_exec_context)s *xc, 542 Trace::InstRecord *traceData) const 543 { 544 Fault fault = NoFault; 545 546 %(mem_decl)s; 547 %(op_decl)s; 548 %(op_rd)s; 549 550 if (%(predicate_test)s) 551 { 552 // ARM instructions will not have a pkt if the predicate is false 553 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 554 555 if (fault == NoFault) { 556 %(memacc_code)s; 557 } 558 559 if (fault == NoFault) { 560 %(op_wb)s; 561 } 562 } 563 564 if (fault == NoFault && machInst.itstateMask != 0) { 565 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 566 } 567 568 return fault; 569 } 570}}; 571 |
572def template StoreCompleteAcc {{ 573 Fault %(class_name)s::completeAcc(PacketPtr pkt, 574 %(CPU_exec_context)s *xc, 575 Trace::InstRecord *traceData) const 576 { 577 Fault fault = NoFault; 578 579 %(op_decl)s; --- 9 unchanged lines hidden (view full) --- 589 if (fault == NoFault && machInst.itstateMask != 0) { 590 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 591 } 592 593 return fault; 594 } 595}}; 596 |
597def template NeonStoreCompleteAcc {{ 598 template <class Element> 599 Fault %(class_name)s<Element>::completeAcc( 600 PacketPtr pkt, %(CPU_exec_context)s *xc, 601 Trace::InstRecord *traceData) const 602 { 603 Fault fault = NoFault; 604 605 %(op_decl)s; 606 %(op_rd)s; 607 608 if (%(predicate_test)s) 609 { 610 if (fault == NoFault) { 611 %(op_wb)s; 612 } 613 } 614 615 if (fault == NoFault && machInst.itstateMask != 0) { 616 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 617 } 618 619 return fault; 620 } 621}}; 622 |
623def template StoreExCompleteAcc {{ 624 Fault %(class_name)s::completeAcc(PacketPtr pkt, 625 %(CPU_exec_context)s *xc, 626 Trace::InstRecord *traceData) const 627 { 628 Fault fault = NoFault; 629 630 %(op_decl)s; --- 319 unchanged lines hidden --- |