1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 65 if (fault == NoFault) { 66 %(postacc_code)s; 67 } 68 69 if (fault == NoFault) { 70 %(op_wb)s; 71 } |
72 } else { 73 xc->setPredicate(false); |
74 } 75 76 if (fault == NoFault && machInst.itstateMask != 0) { 77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 78 } 79 80 return fault; 81 } --- 18 unchanged lines hidden (view full) --- 100 if (fault == NoFault) { 101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 102 memAccessFlags, &memData); 103 } 104 105 if (fault == NoFault) { 106 %(op_wb)s; 107 } |
108 } else { 109 xc->setPredicate(false); |
110 } 111 112 if (fault == NoFault && machInst.itstateMask != 0) { 113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 114 } 115 116 return fault; 117 } --- 45 unchanged lines hidden (view full) --- 163 if (fault == NoFault) { 164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 165 %(memacc_code)s; 166 } 167 168 if (fault == NoFault) { 169 %(op_wb)s; 170 } |
171 } else { 172 xc->setPredicate(false); |
173 } 174 175 if (fault == NoFault && machInst.itstateMask != 0) { 176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 177 } 178 179 return fault; 180 } --- 20 unchanged lines hidden (view full) --- 201 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 202 memAccessFlags, NULL); 203 if (traceData) { traceData->setData(Mem); } 204 } 205 206 if (fault == NoFault) { 207 %(op_wb)s; 208 } |
209 } else { 210 xc->setPredicate(false); |
211 } 212 213 if (fault == NoFault && machInst.itstateMask != 0) { 214 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 215 } 216 217 return fault; 218 } --- 26 unchanged lines hidden (view full) --- 245 246 if (fault == NoFault) { 247 %(postacc_code)s; 248 } 249 250 if (fault == NoFault) { 251 %(op_wb)s; 252 } |
253 } else { 254 xc->setPredicate(false); |
255 } 256 257 if (fault == NoFault && machInst.itstateMask != 0) { 258 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 259 } 260 261 return fault; 262 } --- 21 unchanged lines hidden (view full) --- 284 memAccessFlags, NULL); 285 if (traceData) { traceData->setData(Mem); } 286 } 287 288 // Need to write back any potential address register update 289 if (fault == NoFault) { 290 %(op_wb)s; 291 } |
292 } else { 293 xc->setPredicate(false); |
294 } 295 296 if (fault == NoFault && machInst.itstateMask != 0) { 297 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 298 } 299 300 return fault; 301 } --- 21 unchanged lines hidden (view full) --- 323 memAccessFlags, NULL); 324 if (traceData) { traceData->setData(Mem); } 325 } 326 327 // Need to write back any potential address register update 328 if (fault == NoFault) { 329 %(op_wb)s; 330 } |
331 } else { 332 xc->setPredicate(false); |
333 } 334 335 if (fault == NoFault && machInst.itstateMask != 0) { 336 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 337 } 338 339 return fault; 340 } --- 10 unchanged lines hidden (view full) --- 351 %(op_rd)s; 352 %(ea_code)s; 353 354 if (%(predicate_test)s) 355 { 356 if (fault == NoFault) { 357 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 358 } |
359 } else { 360 xc->setPredicate(false); 361 if (fault == NoFault && machInst.itstateMask != 0) { 362 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 363 } |
364 } 365 366 return fault; 367 } 368}}; 369 370def template LoadCompleteAcc {{ 371 Fault %(class_name)s::completeAcc(PacketPtr pkt, --- 382 unchanged lines hidden --- |