mem.isa (8203:78b9f056d58a) mem.isa (8205:7ecbffb674aa)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template PanicExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 panic("Execute function executed when it shouldn't be!\n");
49 return NoFault;
50 }
51}};
52
53def template PanicInitiateAcc {{
54 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
55 Trace::InstRecord *traceData) const
56 {
57 panic("InitiateAcc function executed when it shouldn't be!\n");
58 return NoFault;
59 }
60}};
61
62def template PanicCompleteAcc {{
63 Fault %(class_name)s::completeAcc(PacketPtr pkt,
64 %(CPU_exec_context)s *xc,
65 Trace::InstRecord *traceData) const
66 {
67 panic("CompleteAcc function executed when it shouldn't be!\n");
68 return NoFault;
69 }
70}};
71
72
73def template SwapExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Addr EA;
78 Fault fault = NoFault;
79
80 %(op_decl)s;
81 uint64_t memData = 0;
82 %(op_rd)s;
83 %(ea_code)s;
84
85 if (%(predicate_test)s)
86 {
87 %(preacc_code)s;
88
89 if (fault == NoFault) {
90 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
91 EA, memAccessFlags, &memData);
92 }
93
94 if (fault == NoFault) {
95 %(postacc_code)s;
96 }
97
98 if (fault == NoFault) {
99 %(op_wb)s;
100 }
101 } else {
102 xc->setPredicate(false);
103 }
104
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template PanicExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 panic("Execute function executed when it shouldn't be!\n");
49 return NoFault;
50 }
51}};
52
53def template PanicInitiateAcc {{
54 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
55 Trace::InstRecord *traceData) const
56 {
57 panic("InitiateAcc function executed when it shouldn't be!\n");
58 return NoFault;
59 }
60}};
61
62def template PanicCompleteAcc {{
63 Fault %(class_name)s::completeAcc(PacketPtr pkt,
64 %(CPU_exec_context)s *xc,
65 Trace::InstRecord *traceData) const
66 {
67 panic("CompleteAcc function executed when it shouldn't be!\n");
68 return NoFault;
69 }
70}};
71
72
73def template SwapExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Addr EA;
78 Fault fault = NoFault;
79
80 %(op_decl)s;
81 uint64_t memData = 0;
82 %(op_rd)s;
83 %(ea_code)s;
84
85 if (%(predicate_test)s)
86 {
87 %(preacc_code)s;
88
89 if (fault == NoFault) {
90 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
91 EA, memAccessFlags, &memData);
92 }
93
94 if (fault == NoFault) {
95 %(postacc_code)s;
96 }
97
98 if (fault == NoFault) {
99 %(op_wb)s;
100 }
101 } else {
102 xc->setPredicate(false);
103 }
104
105 if (fault == NoFault && machInst.itstateMask != 0 &&
106 (!isMicroop() || isLastMicroop())) {
107 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
108 }
109
110 return fault;
111 }
112}};
113
114def template SwapInitiateAcc {{
115 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
116 Trace::InstRecord *traceData) const
117 {
118 Addr EA;
119 Fault fault = NoFault;
120
121 %(op_decl)s;
122 uint64_t memData = 0;
123 %(op_rd)s;
124 %(ea_code)s;
125
126 if (%(predicate_test)s)
127 {
128 %(preacc_code)s;
129
130 if (fault == NoFault) {
131 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
132 memAccessFlags, &memData);
133 }
134 } else {
135 xc->setPredicate(false);
136 }
137
105 return fault;
106 }
107}};
108
109def template SwapInitiateAcc {{
110 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
111 Trace::InstRecord *traceData) const
112 {
113 Addr EA;
114 Fault fault = NoFault;
115
116 %(op_decl)s;
117 uint64_t memData = 0;
118 %(op_rd)s;
119 %(ea_code)s;
120
121 if (%(predicate_test)s)
122 {
123 %(preacc_code)s;
124
125 if (fault == NoFault) {
126 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
127 memAccessFlags, &memData);
128 }
129 } else {
130 xc->setPredicate(false);
131 }
132
138 if (fault == NoFault && machInst.itstateMask != 0 &&
139 (!isMicroop() || isLastMicroop())) {
140 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
141 }
142
143 return fault;
144 }
145}};
146
147def template SwapCompleteAcc {{
148 Fault %(class_name)s::completeAcc(PacketPtr pkt,
149 %(CPU_exec_context)s *xc,
150 Trace::InstRecord *traceData) const
151 {
152 Fault fault = NoFault;
153
154 %(op_decl)s;
155 %(op_rd)s;
156
157 if (%(predicate_test)s)
158 {
159 // ARM instructions will not have a pkt if the predicate is false
160 uint64_t memData = pkt->get<typeof(Mem)>();
161
162 %(postacc_code)s;
163
164 if (fault == NoFault) {
165 %(op_wb)s;
166 }
167 }
168
133 return fault;
134 }
135}};
136
137def template SwapCompleteAcc {{
138 Fault %(class_name)s::completeAcc(PacketPtr pkt,
139 %(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
141 {
142 Fault fault = NoFault;
143
144 %(op_decl)s;
145 %(op_rd)s;
146
147 if (%(predicate_test)s)
148 {
149 // ARM instructions will not have a pkt if the predicate is false
150 uint64_t memData = pkt->get<typeof(Mem)>();
151
152 %(postacc_code)s;
153
154 if (fault == NoFault) {
155 %(op_wb)s;
156 }
157 }
158
169 if (fault == NoFault && machInst.itstateMask != 0) {
170 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
171 }
172
173 return fault;
174 }
175}};
176
177def template LoadExecute {{
178 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
179 Trace::InstRecord *traceData) const
180 {
181 Addr EA;
182 Fault fault = NoFault;
183
184 %(op_decl)s;
185 %(op_rd)s;
186 %(ea_code)s;
187
188 if (%(predicate_test)s)
189 {
190 if (fault == NoFault) {
191 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
192 %(memacc_code)s;
193 }
194
195 if (fault == NoFault) {
196 %(op_wb)s;
197 }
198 } else {
199 xc->setPredicate(false);
200 }
201
159 return fault;
160 }
161}};
162
163def template LoadExecute {{
164 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
165 Trace::InstRecord *traceData) const
166 {
167 Addr EA;
168 Fault fault = NoFault;
169
170 %(op_decl)s;
171 %(op_rd)s;
172 %(ea_code)s;
173
174 if (%(predicate_test)s)
175 {
176 if (fault == NoFault) {
177 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
178 %(memacc_code)s;
179 }
180
181 if (fault == NoFault) {
182 %(op_wb)s;
183 }
184 } else {
185 xc->setPredicate(false);
186 }
187
202 if (fault == NoFault && machInst.itstateMask != 0 &&
203 (!isMicroop() || isLastMicroop())) {
204 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
205 }
206
207 return fault;
208 }
209}};
210
211def template NeonLoadExecute {{
212 template <class Element>
213 Fault %(class_name)s<Element>::execute(
214 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
215 {
216 Addr EA;
217 Fault fault = NoFault;
218
219 %(op_decl)s;
220 %(mem_decl)s;
221 %(op_rd)s;
222 %(ea_code)s;
223
224 MemUnion memUnion;
225 uint8_t *dataPtr = memUnion.bytes;
226
227 if (%(predicate_test)s)
228 {
229 if (fault == NoFault) {
230 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
231 %(memacc_code)s;
232 }
233
234 if (fault == NoFault) {
235 %(op_wb)s;
236 }
237 } else {
238 xc->setPredicate(false);
239 }
240
188 return fault;
189 }
190}};
191
192def template NeonLoadExecute {{
193 template <class Element>
194 Fault %(class_name)s<Element>::execute(
195 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
196 {
197 Addr EA;
198 Fault fault = NoFault;
199
200 %(op_decl)s;
201 %(mem_decl)s;
202 %(op_rd)s;
203 %(ea_code)s;
204
205 MemUnion memUnion;
206 uint8_t *dataPtr = memUnion.bytes;
207
208 if (%(predicate_test)s)
209 {
210 if (fault == NoFault) {
211 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
212 %(memacc_code)s;
213 }
214
215 if (fault == NoFault) {
216 %(op_wb)s;
217 }
218 } else {
219 xc->setPredicate(false);
220 }
221
241 if (fault == NoFault && machInst.itstateMask != 0 &&
242 (!isMicroop() || isLastMicroop())) {
243 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
244 }
245
246 return fault;
247 }
248}};
249
250def template StoreExecute {{
251 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
252 Trace::InstRecord *traceData) const
253 {
254 Addr EA;
255 Fault fault = NoFault;
256
257 %(op_decl)s;
258 %(op_rd)s;
259 %(ea_code)s;
260
261 if (%(predicate_test)s)
262 {
263 if (fault == NoFault) {
264 %(memacc_code)s;
265 }
266
267 if (fault == NoFault) {
268 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
269 memAccessFlags, NULL);
270 }
271
272 if (fault == NoFault) {
273 %(op_wb)s;
274 }
275 } else {
276 xc->setPredicate(false);
277 }
278
222 return fault;
223 }
224}};
225
226def template StoreExecute {{
227 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
228 Trace::InstRecord *traceData) const
229 {
230 Addr EA;
231 Fault fault = NoFault;
232
233 %(op_decl)s;
234 %(op_rd)s;
235 %(ea_code)s;
236
237 if (%(predicate_test)s)
238 {
239 if (fault == NoFault) {
240 %(memacc_code)s;
241 }
242
243 if (fault == NoFault) {
244 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
245 memAccessFlags, NULL);
246 }
247
248 if (fault == NoFault) {
249 %(op_wb)s;
250 }
251 } else {
252 xc->setPredicate(false);
253 }
254
279 if (fault == NoFault && machInst.itstateMask != 0 &&
280 (!isMicroop() || isLastMicroop())) {
281 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
282 }
283
284 return fault;
285 }
286}};
287
288def template NeonStoreExecute {{
289 template <class Element>
290 Fault %(class_name)s<Element>::execute(
291 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
292 {
293 Addr EA;
294 Fault fault = NoFault;
295
296 %(op_decl)s;
297 %(mem_decl)s;
298 %(op_rd)s;
299 %(ea_code)s;
300
301 MemUnion memUnion;
302 uint8_t *dataPtr = memUnion.bytes;
303
304 if (%(predicate_test)s)
305 {
306 if (fault == NoFault) {
307 %(memacc_code)s;
308 }
309
310 if (fault == NoFault) {
311 fault = xc->writeBytes(dataPtr, %(size)d, EA,
312 memAccessFlags, NULL);
313 }
314
315 if (fault == NoFault) {
316 %(op_wb)s;
317 }
318 } else {
319 xc->setPredicate(false);
320 }
321
255 return fault;
256 }
257}};
258
259def template NeonStoreExecute {{
260 template <class Element>
261 Fault %(class_name)s<Element>::execute(
262 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
263 {
264 Addr EA;
265 Fault fault = NoFault;
266
267 %(op_decl)s;
268 %(mem_decl)s;
269 %(op_rd)s;
270 %(ea_code)s;
271
272 MemUnion memUnion;
273 uint8_t *dataPtr = memUnion.bytes;
274
275 if (%(predicate_test)s)
276 {
277 if (fault == NoFault) {
278 %(memacc_code)s;
279 }
280
281 if (fault == NoFault) {
282 fault = xc->writeBytes(dataPtr, %(size)d, EA,
283 memAccessFlags, NULL);
284 }
285
286 if (fault == NoFault) {
287 %(op_wb)s;
288 }
289 } else {
290 xc->setPredicate(false);
291 }
292
322 if (fault == NoFault && machInst.itstateMask != 0 &&
323 (!isMicroop() || isLastMicroop())) {
324 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
325 }
326
327 return fault;
328 }
329}};
330
331def template StoreExExecute {{
332 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
333 Trace::InstRecord *traceData) const
334 {
335 Addr EA;
336 Fault fault = NoFault;
337
338 %(op_decl)s;
339 %(op_rd)s;
340 %(ea_code)s;
341
342 if (%(predicate_test)s)
343 {
344 if (fault == NoFault) {
345 %(memacc_code)s;
346 }
347
348 uint64_t writeResult;
349
350 if (fault == NoFault) {
351 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
352 memAccessFlags, &writeResult);
353 }
354
355 if (fault == NoFault) {
356 %(postacc_code)s;
357 }
358
359 if (fault == NoFault) {
360 %(op_wb)s;
361 }
362 } else {
363 xc->setPredicate(false);
364 }
365
293 return fault;
294 }
295}};
296
297def template StoreExExecute {{
298 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
299 Trace::InstRecord *traceData) const
300 {
301 Addr EA;
302 Fault fault = NoFault;
303
304 %(op_decl)s;
305 %(op_rd)s;
306 %(ea_code)s;
307
308 if (%(predicate_test)s)
309 {
310 if (fault == NoFault) {
311 %(memacc_code)s;
312 }
313
314 uint64_t writeResult;
315
316 if (fault == NoFault) {
317 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
318 memAccessFlags, &writeResult);
319 }
320
321 if (fault == NoFault) {
322 %(postacc_code)s;
323 }
324
325 if (fault == NoFault) {
326 %(op_wb)s;
327 }
328 } else {
329 xc->setPredicate(false);
330 }
331
366 if (fault == NoFault && machInst.itstateMask != 0 &&
367 (!isMicroop() || isLastMicroop())) {
368 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
369 }
370
371 return fault;
372 }
373}};
374
375def template StoreExInitiateAcc {{
376 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
377 Trace::InstRecord *traceData) const
378 {
379 Addr EA;
380 Fault fault = NoFault;
381
382 %(op_decl)s;
383 %(op_rd)s;
384 %(ea_code)s;
385
386 if (%(predicate_test)s)
387 {
388 if (fault == NoFault) {
389 %(memacc_code)s;
390 }
391
392 if (fault == NoFault) {
393 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
394 memAccessFlags, NULL);
395 }
396 } else {
397 xc->setPredicate(false);
398 }
332 return fault;
333 }
334}};
335
336def template StoreExInitiateAcc {{
337 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
338 Trace::InstRecord *traceData) const
339 {
340 Addr EA;
341 Fault fault = NoFault;
342
343 %(op_decl)s;
344 %(op_rd)s;
345 %(ea_code)s;
346
347 if (%(predicate_test)s)
348 {
349 if (fault == NoFault) {
350 %(memacc_code)s;
351 }
352
353 if (fault == NoFault) {
354 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
355 memAccessFlags, NULL);
356 }
357 } else {
358 xc->setPredicate(false);
359 }
399 if (fault == NoFault && machInst.itstateMask != 0 &&
400 (!isMicroop() || isLastMicroop())) {
401 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
402 }
403
404 return fault;
405 }
406}};
407
408def template StoreInitiateAcc {{
409 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
410 Trace::InstRecord *traceData) const
411 {
412 Addr EA;
413 Fault fault = NoFault;
414
415 %(op_decl)s;
416 %(op_rd)s;
417 %(ea_code)s;
418
419 if (%(predicate_test)s)
420 {
421 if (fault == NoFault) {
422 %(memacc_code)s;
423 }
424
425 if (fault == NoFault) {
426 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
427 memAccessFlags, NULL);
428 }
429 } else {
430 xc->setPredicate(false);
431 }
432
360
361 return fault;
362 }
363}};
364
365def template StoreInitiateAcc {{
366 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
367 Trace::InstRecord *traceData) const
368 {
369 Addr EA;
370 Fault fault = NoFault;
371
372 %(op_decl)s;
373 %(op_rd)s;
374 %(ea_code)s;
375
376 if (%(predicate_test)s)
377 {
378 if (fault == NoFault) {
379 %(memacc_code)s;
380 }
381
382 if (fault == NoFault) {
383 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
384 memAccessFlags, NULL);
385 }
386 } else {
387 xc->setPredicate(false);
388 }
389
433 if (fault == NoFault && machInst.itstateMask != 0 &&
434 (!isMicroop() || isLastMicroop())) {
435 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
436 }
437
438 return fault;
439 }
440}};
441
442def template NeonStoreInitiateAcc {{
443 template <class Element>
444 Fault %(class_name)s<Element>::initiateAcc(
445 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
446 {
447 Addr EA;
448 Fault fault = NoFault;
449
450 %(op_decl)s;
451 %(mem_decl)s;
452 %(op_rd)s;
453 %(ea_code)s;
454
455 if (%(predicate_test)s)
456 {
457 MemUnion memUnion;
458 if (fault == NoFault) {
459 %(memacc_code)s;
460 }
461
462 if (fault == NoFault) {
463 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
464 memAccessFlags, NULL);
465 }
466 } else {
467 xc->setPredicate(false);
468 }
469
390 return fault;
391 }
392}};
393
394def template NeonStoreInitiateAcc {{
395 template <class Element>
396 Fault %(class_name)s<Element>::initiateAcc(
397 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
398 {
399 Addr EA;
400 Fault fault = NoFault;
401
402 %(op_decl)s;
403 %(mem_decl)s;
404 %(op_rd)s;
405 %(ea_code)s;
406
407 if (%(predicate_test)s)
408 {
409 MemUnion memUnion;
410 if (fault == NoFault) {
411 %(memacc_code)s;
412 }
413
414 if (fault == NoFault) {
415 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
416 memAccessFlags, NULL);
417 }
418 } else {
419 xc->setPredicate(false);
420 }
421
470 if (fault == NoFault && machInst.itstateMask != 0 &&
471 (!isMicroop() || isLastMicroop())) {
472 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
473 }
474
475 return fault;
476 }
477}};
478
479def template LoadInitiateAcc {{
480 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
481 Trace::InstRecord *traceData) const
482 {
483 Addr EA;
484 Fault fault = NoFault;
485
486 %(op_src_decl)s;
487 %(op_rd)s;
488 %(ea_code)s;
489
490 if (%(predicate_test)s)
491 {
492 if (fault == NoFault) {
493 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
494 }
495 } else {
496 xc->setPredicate(false);
422 return fault;
423 }
424}};
425
426def template LoadInitiateAcc {{
427 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
428 Trace::InstRecord *traceData) const
429 {
430 Addr EA;
431 Fault fault = NoFault;
432
433 %(op_src_decl)s;
434 %(op_rd)s;
435 %(ea_code)s;
436
437 if (%(predicate_test)s)
438 {
439 if (fault == NoFault) {
440 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
441 }
442 } else {
443 xc->setPredicate(false);
497 if (fault == NoFault && machInst.itstateMask != 0 &&
498 (!isMicroop() || isLastMicroop())) {
499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
500 }
501 }
502
503 return fault;
504 }
505}};
506
507def template NeonLoadInitiateAcc {{
508 template <class Element>
509 Fault %(class_name)s<Element>::initiateAcc(
510 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
511 {
512 Addr EA;
513 Fault fault = NoFault;
514
515 %(op_src_decl)s;
516 %(op_rd)s;
517 %(ea_code)s;
518
519 if (%(predicate_test)s)
520 {
521 if (fault == NoFault) {
522 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
523 }
524 } else {
525 xc->setPredicate(false);
444 }
445
446 return fault;
447 }
448}};
449
450def template NeonLoadInitiateAcc {{
451 template <class Element>
452 Fault %(class_name)s<Element>::initiateAcc(
453 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
454 {
455 Addr EA;
456 Fault fault = NoFault;
457
458 %(op_src_decl)s;
459 %(op_rd)s;
460 %(ea_code)s;
461
462 if (%(predicate_test)s)
463 {
464 if (fault == NoFault) {
465 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
466 }
467 } else {
468 xc->setPredicate(false);
526 if (fault == NoFault && machInst.itstateMask != 0 &&
527 (!isMicroop() || isLastMicroop())) {
528 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
529 }
530 }
531
532 return fault;
533 }
534}};
535
536def template LoadCompleteAcc {{
537 Fault %(class_name)s::completeAcc(PacketPtr pkt,
538 %(CPU_exec_context)s *xc,
539 Trace::InstRecord *traceData) const
540 {
541 Fault fault = NoFault;
542
543 %(op_decl)s;
544 %(op_rd)s;
545
546 if (%(predicate_test)s)
547 {
548 // ARM instructions will not have a pkt if the predicate is false
549 Mem = pkt->get<typeof(Mem)>();
550
551 if (fault == NoFault) {
552 %(memacc_code)s;
553 }
554
555 if (fault == NoFault) {
556 %(op_wb)s;
557 }
558 }
559
469 }
470
471 return fault;
472 }
473}};
474
475def template LoadCompleteAcc {{
476 Fault %(class_name)s::completeAcc(PacketPtr pkt,
477 %(CPU_exec_context)s *xc,
478 Trace::InstRecord *traceData) const
479 {
480 Fault fault = NoFault;
481
482 %(op_decl)s;
483 %(op_rd)s;
484
485 if (%(predicate_test)s)
486 {
487 // ARM instructions will not have a pkt if the predicate is false
488 Mem = pkt->get<typeof(Mem)>();
489
490 if (fault == NoFault) {
491 %(memacc_code)s;
492 }
493
494 if (fault == NoFault) {
495 %(op_wb)s;
496 }
497 }
498
560 if (fault == NoFault && machInst.itstateMask != 0) {
561 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
562 }
563
564 return fault;
565 }
566}};
567
568def template NeonLoadCompleteAcc {{
569 template <class Element>
570 Fault %(class_name)s<Element>::completeAcc(
571 PacketPtr pkt, %(CPU_exec_context)s *xc,
572 Trace::InstRecord *traceData) const
573 {
574 Fault fault = NoFault;
575
576 %(mem_decl)s;
577 %(op_decl)s;
578 %(op_rd)s;
579
580 if (%(predicate_test)s)
581 {
582 // ARM instructions will not have a pkt if the predicate is false
583 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
584
585 if (fault == NoFault) {
586 %(memacc_code)s;
587 }
588
589 if (fault == NoFault) {
590 %(op_wb)s;
591 }
592 }
593
499 return fault;
500 }
501}};
502
503def template NeonLoadCompleteAcc {{
504 template <class Element>
505 Fault %(class_name)s<Element>::completeAcc(
506 PacketPtr pkt, %(CPU_exec_context)s *xc,
507 Trace::InstRecord *traceData) const
508 {
509 Fault fault = NoFault;
510
511 %(mem_decl)s;
512 %(op_decl)s;
513 %(op_rd)s;
514
515 if (%(predicate_test)s)
516 {
517 // ARM instructions will not have a pkt if the predicate is false
518 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
519
520 if (fault == NoFault) {
521 %(memacc_code)s;
522 }
523
524 if (fault == NoFault) {
525 %(op_wb)s;
526 }
527 }
528
594 if (fault == NoFault && machInst.itstateMask != 0) {
595 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
596 }
597
598 return fault;
599 }
600}};
601
602def template StoreCompleteAcc {{
603 Fault %(class_name)s::completeAcc(PacketPtr pkt,
604 %(CPU_exec_context)s *xc,
605 Trace::InstRecord *traceData) const
606 {
529 return fault;
530 }
531}};
532
533def template StoreCompleteAcc {{
534 Fault %(class_name)s::completeAcc(PacketPtr pkt,
535 %(CPU_exec_context)s *xc,
536 Trace::InstRecord *traceData) const
537 {
607 if (machInst.itstateMask != 0) {
608 warn_once("Complete acc isn't called on normal stores in O3.");
609 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
610 }
611 return NoFault;
612 }
613}};
614
615def template NeonStoreCompleteAcc {{
616 template <class Element>
617 Fault %(class_name)s<Element>::completeAcc(
618 PacketPtr pkt, %(CPU_exec_context)s *xc,
619 Trace::InstRecord *traceData) const
620 {
538 return NoFault;
539 }
540}};
541
542def template NeonStoreCompleteAcc {{
543 template <class Element>
544 Fault %(class_name)s<Element>::completeAcc(
545 PacketPtr pkt, %(CPU_exec_context)s *xc,
546 Trace::InstRecord *traceData) const
547 {
621 if (machInst.itstateMask != 0) {
622 warn_once("Complete acc isn't called on normal stores in O3.");
623 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
624 }
625 return NoFault;
626 }
627}};
628
629def template StoreExCompleteAcc {{
630 Fault %(class_name)s::completeAcc(PacketPtr pkt,
631 %(CPU_exec_context)s *xc,
632 Trace::InstRecord *traceData) const
633 {
634 Fault fault = NoFault;
635
636 %(op_decl)s;
637 %(op_rd)s;
638
639 if (%(predicate_test)s)
640 {
641 uint64_t writeResult = pkt->req->getExtraData();
642 %(postacc_code)s;
643
644 if (fault == NoFault) {
645 %(op_wb)s;
646 }
647 }
648
548 return NoFault;
549 }
550}};
551
552def template StoreExCompleteAcc {{
553 Fault %(class_name)s::completeAcc(PacketPtr pkt,
554 %(CPU_exec_context)s *xc,
555 Trace::InstRecord *traceData) const
556 {
557 Fault fault = NoFault;
558
559 %(op_decl)s;
560 %(op_rd)s;
561
562 if (%(predicate_test)s)
563 {
564 uint64_t writeResult = pkt->req->getExtraData();
565 %(postacc_code)s;
566
567 if (fault == NoFault) {
568 %(op_wb)s;
569 }
570 }
571
649 if (fault == NoFault && machInst.itstateMask != 0) {
650 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
651 }
652
653 return fault;
654 }
655}};
656
657def template RfeDeclare {{
658 /**
659 * Static instruction class for "%(mnemonic)s".
660 */
661 class %(class_name)s : public %(base_class)s
662 {
663 public:
664
665 /// Constructor.
666 %(class_name)s(ExtMachInst machInst,
667 uint32_t _base, int _mode, bool _wb);
668
669 %(BasicExecDeclare)s
670
671 %(InitiateAccDeclare)s
672
673 %(CompleteAccDeclare)s
674 };
675}};
676
677def template SrsDeclare {{
678 /**
679 * Static instruction class for "%(mnemonic)s".
680 */
681 class %(class_name)s : public %(base_class)s
682 {
683 public:
684
685 /// Constructor.
686 %(class_name)s(ExtMachInst machInst,
687 uint32_t _regMode, int _mode, bool _wb);
688
689 %(BasicExecDeclare)s
690
691 %(InitiateAccDeclare)s
692
693 %(CompleteAccDeclare)s
694 };
695}};
696
697def template SwapDeclare {{
698 /**
699 * Static instruction class for "%(mnemonic)s".
700 */
701 class %(class_name)s : public %(base_class)s
702 {
703 public:
704
705 /// Constructor.
706 %(class_name)s(ExtMachInst machInst,
707 uint32_t _dest, uint32_t _op1, uint32_t _base);
708
709 %(BasicExecDeclare)s
710
711 %(InitiateAccDeclare)s
712
713 %(CompleteAccDeclare)s
714 };
715}};
716
717def template LoadStoreDImmDeclare {{
718 /**
719 * Static instruction class for "%(mnemonic)s".
720 */
721 class %(class_name)s : public %(base_class)s
722 {
723 public:
724
725 /// Constructor.
726 %(class_name)s(ExtMachInst machInst,
727 uint32_t _dest, uint32_t _dest2,
728 uint32_t _base, bool _add, int32_t _imm);
729
730 %(BasicExecDeclare)s
731
732 %(InitiateAccDeclare)s
733
734 %(CompleteAccDeclare)s
735 };
736}};
737
738def template StoreExDImmDeclare {{
739 /**
740 * Static instruction class for "%(mnemonic)s".
741 */
742 class %(class_name)s : public %(base_class)s
743 {
744 public:
745
746 /// Constructor.
747 %(class_name)s(ExtMachInst machInst,
748 uint32_t _result, uint32_t _dest, uint32_t _dest2,
749 uint32_t _base, bool _add, int32_t _imm);
750
751 %(BasicExecDeclare)s
752
753 %(InitiateAccDeclare)s
754
755 %(CompleteAccDeclare)s
756 };
757}};
758
759def template LoadStoreImmDeclare {{
760 /**
761 * Static instruction class for "%(mnemonic)s".
762 */
763 class %(class_name)s : public %(base_class)s
764 {
765 public:
766
767 /// Constructor.
768 %(class_name)s(ExtMachInst machInst,
769 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
770
771 %(BasicExecDeclare)s
772
773 %(InitiateAccDeclare)s
774
775 %(CompleteAccDeclare)s
776 };
777}};
778
779def template StoreExImmDeclare {{
780 /**
781 * Static instruction class for "%(mnemonic)s".
782 */
783 class %(class_name)s : public %(base_class)s
784 {
785 public:
786
787 /// Constructor.
788 %(class_name)s(ExtMachInst machInst,
789 uint32_t _result, uint32_t _dest, uint32_t _base,
790 bool _add, int32_t _imm);
791
792 %(BasicExecDeclare)s
793
794 %(InitiateAccDeclare)s
795
796 %(CompleteAccDeclare)s
797 };
798}};
799
800def template StoreDRegDeclare {{
801 /**
802 * Static instruction class for "%(mnemonic)s".
803 */
804 class %(class_name)s : public %(base_class)s
805 {
806 public:
807
808 /// Constructor.
809 %(class_name)s(ExtMachInst machInst,
810 uint32_t _dest, uint32_t _dest2,
811 uint32_t _base, bool _add,
812 int32_t _shiftAmt, uint32_t _shiftType,
813 uint32_t _index);
814
815 %(BasicExecDeclare)s
816
817 %(InitiateAccDeclare)s
818
819 %(CompleteAccDeclare)s
820 };
821}};
822
823def template StoreRegDeclare {{
824 /**
825 * Static instruction class for "%(mnemonic)s".
826 */
827 class %(class_name)s : public %(base_class)s
828 {
829 public:
830
831 /// Constructor.
832 %(class_name)s(ExtMachInst machInst,
833 uint32_t _dest, uint32_t _base, bool _add,
834 int32_t _shiftAmt, uint32_t _shiftType,
835 uint32_t _index);
836
837 %(BasicExecDeclare)s
838
839 %(InitiateAccDeclare)s
840
841 %(CompleteAccDeclare)s
842 };
843}};
844
845def template LoadDRegDeclare {{
846 /**
847 * Static instruction class for "%(mnemonic)s".
848 */
849 class %(class_name)s : public %(base_class)s
850 {
851 public:
852
853 /// Constructor.
854 %(class_name)s(ExtMachInst machInst,
855 uint32_t _dest, uint32_t _dest2,
856 uint32_t _base, bool _add,
857 int32_t _shiftAmt, uint32_t _shiftType,
858 uint32_t _index);
859
860 %(BasicExecDeclare)s
861
862 %(InitiateAccDeclare)s
863
864 %(CompleteAccDeclare)s
865 };
866}};
867
868def template LoadRegDeclare {{
869 /**
870 * Static instruction class for "%(mnemonic)s".
871 */
872 class %(class_name)s : public %(base_class)s
873 {
874 public:
875
876 /// Constructor.
877 %(class_name)s(ExtMachInst machInst,
878 uint32_t _dest, uint32_t _base, bool _add,
879 int32_t _shiftAmt, uint32_t _shiftType,
880 uint32_t _index);
881
882 %(BasicExecDeclare)s
883
884 %(InitiateAccDeclare)s
885
886 %(CompleteAccDeclare)s
887 };
888}};
889
890def template LoadImmDeclare {{
891 /**
892 * Static instruction class for "%(mnemonic)s".
893 */
894 class %(class_name)s : public %(base_class)s
895 {
896 public:
897
898 /// Constructor.
899 %(class_name)s(ExtMachInst machInst,
900 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
901
902 %(BasicExecDeclare)s
903
904 %(InitiateAccDeclare)s
905
906 %(CompleteAccDeclare)s
907 };
908}};
909
910def template InitiateAccDeclare {{
911 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
912}};
913
914def template CompleteAccDeclare {{
915 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
916}};
917
918def template RfeConstructor {{
919 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
920 uint32_t _base, int _mode, bool _wb)
921 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
922 (IntRegIndex)_base, (AddrMode)_mode, _wb)
923 {
924 %(constructor)s;
925 if (!(condCode == COND_AL || condCode == COND_UC)) {
926 for (int x = 0; x < _numDestRegs; x++) {
927 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
928 }
929 }
930#if %(use_uops)d
931 uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
932 int uopIdx = 0;
933 uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
934 uops[uopIdx]->setDelayedCommit();
935#if %(use_wb)d
936 uops[++uopIdx] = new %(wb_decl)s;
937 uops[uopIdx]->setDelayedCommit();
938#endif
939#if %(use_pc)d
940 uops[++uopIdx] = new %(pc_decl)s;
941#endif
942 uops[uopIdx]->setLastMicroop();
943#endif
944 }
945}};
946
947def template SrsConstructor {{
948 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
949 uint32_t _regMode, int _mode, bool _wb)
950 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
951 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
952 {
953 %(constructor)s;
954 if (!(condCode == COND_AL || condCode == COND_UC)) {
955 for (int x = 0; x < _numDestRegs; x++) {
956 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
957 }
958 }
959#if %(use_uops)d
960 assert(numMicroops >= 2);
961 uops = new StaticInstPtr[numMicroops];
962 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
963 uops[0]->setDelayedCommit();
964 uops[1] = new %(wb_decl)s;
965 uops[1]->setLastMicroop();
966#endif
967 }
968}};
969
970def template SwapConstructor {{
971 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
972 uint32_t _dest, uint32_t _op1, uint32_t _base)
973 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
974 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
975 {
976 %(constructor)s;
977 if (!(condCode == COND_AL || condCode == COND_UC)) {
978 for (int x = 0; x < _numDestRegs; x++) {
979 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
980 }
981 }
982 }
983}};
984
985def template LoadStoreDImmConstructor {{
986 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
987 uint32_t _dest, uint32_t _dest2,
988 uint32_t _base, bool _add, int32_t _imm)
989 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
990 (IntRegIndex)_dest, (IntRegIndex)_dest2,
991 (IntRegIndex)_base, _add, _imm)
992 {
993 %(constructor)s;
994 if (!(condCode == COND_AL || condCode == COND_UC)) {
995 for (int x = 0; x < _numDestRegs; x++) {
996 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
997 }
998 }
999#if %(use_uops)d
1000 assert(numMicroops >= 2);
1001 uops = new StaticInstPtr[numMicroops];
1002 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
1003 uops[0]->setDelayedCommit();
1004 uops[1] = new %(wb_decl)s;
1005 uops[1]->setLastMicroop();
1006#endif
1007 }
1008}};
1009
1010def template StoreExDImmConstructor {{
1011 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1012 uint32_t _result, uint32_t _dest, uint32_t _dest2,
1013 uint32_t _base, bool _add, int32_t _imm)
1014 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1015 (IntRegIndex)_result,
1016 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1017 (IntRegIndex)_base, _add, _imm)
1018 {
1019 %(constructor)s;
1020 if (!(condCode == COND_AL || condCode == COND_UC)) {
1021 for (int x = 0; x < _numDestRegs; x++) {
1022 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1023 }
1024 }
1025#if %(use_uops)d
1026 assert(numMicroops >= 2);
1027 uops = new StaticInstPtr[numMicroops];
1028 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
1029 _base, _add, _imm);
1030 uops[0]->setDelayedCommit();
1031 uops[1] = new %(wb_decl)s;
1032 uops[1]->setLastMicroop();
1033#endif
1034 }
1035}};
1036
1037def template LoadStoreImmConstructor {{
1038 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1039 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1040 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1041 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1042 {
1043 %(constructor)s;
1044 if (!(condCode == COND_AL || condCode == COND_UC)) {
1045 for (int x = 0; x < _numDestRegs; x++) {
1046 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1047 }
1048 }
1049#if %(use_uops)d
1050 assert(numMicroops >= 2);
1051 uops = new StaticInstPtr[numMicroops];
1052 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1053 uops[0]->setDelayedCommit();
1054 uops[1] = new %(wb_decl)s;
1055 uops[1]->setLastMicroop();
1056#endif
1057 }
1058}};
1059
1060def template StoreExImmConstructor {{
1061 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1062 uint32_t _result, uint32_t _dest, uint32_t _base,
1063 bool _add, int32_t _imm)
1064 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1065 (IntRegIndex)_result, (IntRegIndex)_dest,
1066 (IntRegIndex)_base, _add, _imm)
1067 {
1068 %(constructor)s;
1069 if (!(condCode == COND_AL || condCode == COND_UC)) {
1070 for (int x = 0; x < _numDestRegs; x++) {
1071 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1072 }
1073 }
1074#if %(use_uops)d
1075 assert(numMicroops >= 2);
1076 uops = new StaticInstPtr[numMicroops];
1077 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1078 _base, _add, _imm);
1079 uops[0]->setDelayedCommit();
1080 uops[1] = new %(wb_decl)s;
1081 uops[1]->setLastMicroop();
1082#endif
1083 }
1084}};
1085
1086def template StoreDRegConstructor {{
1087 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1088 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1089 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1090 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1091 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1092 (IntRegIndex)_base, _add,
1093 _shiftAmt, (ArmShiftType)_shiftType,
1094 (IntRegIndex)_index)
1095 {
1096 %(constructor)s;
1097 if (!(condCode == COND_AL || condCode == COND_UC)) {
1098 for (int x = 0; x < _numDestRegs; x++) {
1099 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1100 }
1101 }
1102#if %(use_uops)d
1103 assert(numMicroops >= 2);
1104 uops = new StaticInstPtr[numMicroops];
1105 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1106 _shiftAmt, _shiftType, _index);
1107 uops[0]->setDelayedCommit();
1108 uops[1] = new %(wb_decl)s;
1109 uops[1]->setLastMicroop();
1110#endif
1111 }
1112}};
1113
1114def template StoreRegConstructor {{
1115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1116 uint32_t _dest, uint32_t _base, bool _add,
1117 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1118 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1119 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1120 _shiftAmt, (ArmShiftType)_shiftType,
1121 (IntRegIndex)_index)
1122 {
1123 %(constructor)s;
1124 if (!(condCode == COND_AL || condCode == COND_UC)) {
1125 for (int x = 0; x < _numDestRegs; x++) {
1126 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1127 }
1128 }
1129#if %(use_uops)d
1130 assert(numMicroops >= 2);
1131 uops = new StaticInstPtr[numMicroops];
1132 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1133 _shiftAmt, _shiftType, _index);
1134 uops[0]->setDelayedCommit();
1135 uops[1] = new %(wb_decl)s;
1136 uops[1]->setLastMicroop();
1137#endif
1138 }
1139}};
1140
1141def template LoadDRegConstructor {{
1142 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1143 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1144 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1145 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1146 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1147 (IntRegIndex)_base, _add,
1148 _shiftAmt, (ArmShiftType)_shiftType,
1149 (IntRegIndex)_index)
1150 {
1151 %(constructor)s;
1152 if (!(condCode == COND_AL || condCode == COND_UC)) {
1153 for (int x = 0; x < _numDestRegs; x++) {
1154 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1155 }
1156 }
1157#if %(use_uops)d
1158 assert(numMicroops >= 2);
1159 uops = new StaticInstPtr[numMicroops];
1160 if ((_dest == _index) || (_dest2 == _index)) {
1161 IntRegIndex wbIndexReg = INTREG_UREG0;
1162 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1163 uops[0]->setDelayedCommit();
1164 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1165 _shiftAmt, _shiftType, _index);
1166 uops[1]->setDelayedCommit();
1167 uops[2] = new %(wb_decl)s;
1168 uops[2]->setLastMicroop();
1169 } else {
1170 IntRegIndex wbIndexReg = index;
1171 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1172 _shiftAmt, _shiftType, _index);
1173 uops[0]->setDelayedCommit();
1174 uops[1] = new %(wb_decl)s;
1175 uops[1]->setLastMicroop();
1176 }
1177#endif
1178 }
1179}};
1180
1181def template LoadRegConstructor {{
1182 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1183 uint32_t _dest, uint32_t _base, bool _add,
1184 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1185 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1186 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1187 _shiftAmt, (ArmShiftType)_shiftType,
1188 (IntRegIndex)_index)
1189 {
1190 %(constructor)s;
1191 bool conditional = false;
1192 if (!(condCode == COND_AL || condCode == COND_UC)) {
1193 conditional = true;
1194 for (int x = 0; x < _numDestRegs; x++) {
1195 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1196 }
1197 }
1198#if %(use_uops)d
1199 assert(numMicroops >= 2);
1200 uops = new StaticInstPtr[numMicroops];
1201 if (_dest == INTREG_PC) {
1202 IntRegIndex wbIndexReg = index;
1203 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1204 _shiftAmt, _shiftType, _index);
1205 uops[0]->setDelayedCommit();
1206 uops[1] = new %(wb_decl)s;
1207 uops[1]->setDelayedCommit();
1208 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1209 uops[2]->setFlag(StaticInst::IsControl);
1210 uops[2]->setFlag(StaticInst::IsIndirectControl);
1211 if (conditional)
1212 uops[2]->setFlag(StaticInst::IsCondControl);
1213 else
1214 uops[2]->setFlag(StaticInst::IsUncondControl);
1215 uops[2]->setLastMicroop();
1216 } else if(_dest == _index) {
1217 IntRegIndex wbIndexReg = INTREG_UREG0;
1218 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1219 uops[0]->setDelayedCommit();
1220 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1221 _shiftAmt, _shiftType, _index);
1222 uops[1]->setDelayedCommit();
1223 uops[2] = new %(wb_decl)s;
1224 uops[2]->setLastMicroop();
1225 } else {
1226 IntRegIndex wbIndexReg = index;
1227 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1228 _shiftAmt, _shiftType, _index);
1229 uops[0]->setDelayedCommit();
1230 uops[1] = new %(wb_decl)s;
1231 uops[1]->setLastMicroop();
1232
1233 }
1234#endif
1235 }
1236}};
1237
1238def template LoadImmConstructor {{
1239 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1240 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1241 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1242 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1243 {
1244 %(constructor)s;
1245 bool conditional = false;
1246 if (!(condCode == COND_AL || condCode == COND_UC)) {
1247 conditional = true;
1248 for (int x = 0; x < _numDestRegs; x++) {
1249 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1250 }
1251 }
1252#if %(use_uops)d
1253 assert(numMicroops >= 2);
1254 uops = new StaticInstPtr[numMicroops];
1255 if (_dest == INTREG_PC) {
1256 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1257 _imm);
1258 uops[0]->setDelayedCommit();
1259 uops[1] = new %(wb_decl)s;
1260 uops[1]->setDelayedCommit();
1261 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1262 uops[2]->setFlag(StaticInst::IsControl);
1263 uops[2]->setFlag(StaticInst::IsIndirectControl);
1264 if (conditional)
1265 uops[2]->setFlag(StaticInst::IsCondControl);
1266 else
1267 uops[2]->setFlag(StaticInst::IsUncondControl);
1268 if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
1269 uops[2]->setFlag(StaticInst::IsReturn);
1270 uops[2]->setLastMicroop();
1271 } else {
1272 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1273 uops[0]->setDelayedCommit();
1274 uops[1] = new %(wb_decl)s;
1275 uops[1]->setLastMicroop();
1276 }
1277#endif
1278 }
1279}};
1280
572 return fault;
573 }
574}};
575
576def template RfeDeclare {{
577 /**
578 * Static instruction class for "%(mnemonic)s".
579 */
580 class %(class_name)s : public %(base_class)s
581 {
582 public:
583
584 /// Constructor.
585 %(class_name)s(ExtMachInst machInst,
586 uint32_t _base, int _mode, bool _wb);
587
588 %(BasicExecDeclare)s
589
590 %(InitiateAccDeclare)s
591
592 %(CompleteAccDeclare)s
593 };
594}};
595
596def template SrsDeclare {{
597 /**
598 * Static instruction class for "%(mnemonic)s".
599 */
600 class %(class_name)s : public %(base_class)s
601 {
602 public:
603
604 /// Constructor.
605 %(class_name)s(ExtMachInst machInst,
606 uint32_t _regMode, int _mode, bool _wb);
607
608 %(BasicExecDeclare)s
609
610 %(InitiateAccDeclare)s
611
612 %(CompleteAccDeclare)s
613 };
614}};
615
616def template SwapDeclare {{
617 /**
618 * Static instruction class for "%(mnemonic)s".
619 */
620 class %(class_name)s : public %(base_class)s
621 {
622 public:
623
624 /// Constructor.
625 %(class_name)s(ExtMachInst machInst,
626 uint32_t _dest, uint32_t _op1, uint32_t _base);
627
628 %(BasicExecDeclare)s
629
630 %(InitiateAccDeclare)s
631
632 %(CompleteAccDeclare)s
633 };
634}};
635
636def template LoadStoreDImmDeclare {{
637 /**
638 * Static instruction class for "%(mnemonic)s".
639 */
640 class %(class_name)s : public %(base_class)s
641 {
642 public:
643
644 /// Constructor.
645 %(class_name)s(ExtMachInst machInst,
646 uint32_t _dest, uint32_t _dest2,
647 uint32_t _base, bool _add, int32_t _imm);
648
649 %(BasicExecDeclare)s
650
651 %(InitiateAccDeclare)s
652
653 %(CompleteAccDeclare)s
654 };
655}};
656
657def template StoreExDImmDeclare {{
658 /**
659 * Static instruction class for "%(mnemonic)s".
660 */
661 class %(class_name)s : public %(base_class)s
662 {
663 public:
664
665 /// Constructor.
666 %(class_name)s(ExtMachInst machInst,
667 uint32_t _result, uint32_t _dest, uint32_t _dest2,
668 uint32_t _base, bool _add, int32_t _imm);
669
670 %(BasicExecDeclare)s
671
672 %(InitiateAccDeclare)s
673
674 %(CompleteAccDeclare)s
675 };
676}};
677
678def template LoadStoreImmDeclare {{
679 /**
680 * Static instruction class for "%(mnemonic)s".
681 */
682 class %(class_name)s : public %(base_class)s
683 {
684 public:
685
686 /// Constructor.
687 %(class_name)s(ExtMachInst machInst,
688 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
689
690 %(BasicExecDeclare)s
691
692 %(InitiateAccDeclare)s
693
694 %(CompleteAccDeclare)s
695 };
696}};
697
698def template StoreExImmDeclare {{
699 /**
700 * Static instruction class for "%(mnemonic)s".
701 */
702 class %(class_name)s : public %(base_class)s
703 {
704 public:
705
706 /// Constructor.
707 %(class_name)s(ExtMachInst machInst,
708 uint32_t _result, uint32_t _dest, uint32_t _base,
709 bool _add, int32_t _imm);
710
711 %(BasicExecDeclare)s
712
713 %(InitiateAccDeclare)s
714
715 %(CompleteAccDeclare)s
716 };
717}};
718
719def template StoreDRegDeclare {{
720 /**
721 * Static instruction class for "%(mnemonic)s".
722 */
723 class %(class_name)s : public %(base_class)s
724 {
725 public:
726
727 /// Constructor.
728 %(class_name)s(ExtMachInst machInst,
729 uint32_t _dest, uint32_t _dest2,
730 uint32_t _base, bool _add,
731 int32_t _shiftAmt, uint32_t _shiftType,
732 uint32_t _index);
733
734 %(BasicExecDeclare)s
735
736 %(InitiateAccDeclare)s
737
738 %(CompleteAccDeclare)s
739 };
740}};
741
742def template StoreRegDeclare {{
743 /**
744 * Static instruction class for "%(mnemonic)s".
745 */
746 class %(class_name)s : public %(base_class)s
747 {
748 public:
749
750 /// Constructor.
751 %(class_name)s(ExtMachInst machInst,
752 uint32_t _dest, uint32_t _base, bool _add,
753 int32_t _shiftAmt, uint32_t _shiftType,
754 uint32_t _index);
755
756 %(BasicExecDeclare)s
757
758 %(InitiateAccDeclare)s
759
760 %(CompleteAccDeclare)s
761 };
762}};
763
764def template LoadDRegDeclare {{
765 /**
766 * Static instruction class for "%(mnemonic)s".
767 */
768 class %(class_name)s : public %(base_class)s
769 {
770 public:
771
772 /// Constructor.
773 %(class_name)s(ExtMachInst machInst,
774 uint32_t _dest, uint32_t _dest2,
775 uint32_t _base, bool _add,
776 int32_t _shiftAmt, uint32_t _shiftType,
777 uint32_t _index);
778
779 %(BasicExecDeclare)s
780
781 %(InitiateAccDeclare)s
782
783 %(CompleteAccDeclare)s
784 };
785}};
786
787def template LoadRegDeclare {{
788 /**
789 * Static instruction class for "%(mnemonic)s".
790 */
791 class %(class_name)s : public %(base_class)s
792 {
793 public:
794
795 /// Constructor.
796 %(class_name)s(ExtMachInst machInst,
797 uint32_t _dest, uint32_t _base, bool _add,
798 int32_t _shiftAmt, uint32_t _shiftType,
799 uint32_t _index);
800
801 %(BasicExecDeclare)s
802
803 %(InitiateAccDeclare)s
804
805 %(CompleteAccDeclare)s
806 };
807}};
808
809def template LoadImmDeclare {{
810 /**
811 * Static instruction class for "%(mnemonic)s".
812 */
813 class %(class_name)s : public %(base_class)s
814 {
815 public:
816
817 /// Constructor.
818 %(class_name)s(ExtMachInst machInst,
819 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
820
821 %(BasicExecDeclare)s
822
823 %(InitiateAccDeclare)s
824
825 %(CompleteAccDeclare)s
826 };
827}};
828
829def template InitiateAccDeclare {{
830 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
831}};
832
833def template CompleteAccDeclare {{
834 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
835}};
836
837def template RfeConstructor {{
838 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
839 uint32_t _base, int _mode, bool _wb)
840 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
841 (IntRegIndex)_base, (AddrMode)_mode, _wb)
842 {
843 %(constructor)s;
844 if (!(condCode == COND_AL || condCode == COND_UC)) {
845 for (int x = 0; x < _numDestRegs; x++) {
846 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
847 }
848 }
849#if %(use_uops)d
850 uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
851 int uopIdx = 0;
852 uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
853 uops[uopIdx]->setDelayedCommit();
854#if %(use_wb)d
855 uops[++uopIdx] = new %(wb_decl)s;
856 uops[uopIdx]->setDelayedCommit();
857#endif
858#if %(use_pc)d
859 uops[++uopIdx] = new %(pc_decl)s;
860#endif
861 uops[uopIdx]->setLastMicroop();
862#endif
863 }
864}};
865
866def template SrsConstructor {{
867 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
868 uint32_t _regMode, int _mode, bool _wb)
869 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
870 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
871 {
872 %(constructor)s;
873 if (!(condCode == COND_AL || condCode == COND_UC)) {
874 for (int x = 0; x < _numDestRegs; x++) {
875 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
876 }
877 }
878#if %(use_uops)d
879 assert(numMicroops >= 2);
880 uops = new StaticInstPtr[numMicroops];
881 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
882 uops[0]->setDelayedCommit();
883 uops[1] = new %(wb_decl)s;
884 uops[1]->setLastMicroop();
885#endif
886 }
887}};
888
889def template SwapConstructor {{
890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
891 uint32_t _dest, uint32_t _op1, uint32_t _base)
892 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
893 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
894 {
895 %(constructor)s;
896 if (!(condCode == COND_AL || condCode == COND_UC)) {
897 for (int x = 0; x < _numDestRegs; x++) {
898 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
899 }
900 }
901 }
902}};
903
904def template LoadStoreDImmConstructor {{
905 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
906 uint32_t _dest, uint32_t _dest2,
907 uint32_t _base, bool _add, int32_t _imm)
908 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
909 (IntRegIndex)_dest, (IntRegIndex)_dest2,
910 (IntRegIndex)_base, _add, _imm)
911 {
912 %(constructor)s;
913 if (!(condCode == COND_AL || condCode == COND_UC)) {
914 for (int x = 0; x < _numDestRegs; x++) {
915 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
916 }
917 }
918#if %(use_uops)d
919 assert(numMicroops >= 2);
920 uops = new StaticInstPtr[numMicroops];
921 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
922 uops[0]->setDelayedCommit();
923 uops[1] = new %(wb_decl)s;
924 uops[1]->setLastMicroop();
925#endif
926 }
927}};
928
929def template StoreExDImmConstructor {{
930 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
931 uint32_t _result, uint32_t _dest, uint32_t _dest2,
932 uint32_t _base, bool _add, int32_t _imm)
933 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
934 (IntRegIndex)_result,
935 (IntRegIndex)_dest, (IntRegIndex)_dest2,
936 (IntRegIndex)_base, _add, _imm)
937 {
938 %(constructor)s;
939 if (!(condCode == COND_AL || condCode == COND_UC)) {
940 for (int x = 0; x < _numDestRegs; x++) {
941 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
942 }
943 }
944#if %(use_uops)d
945 assert(numMicroops >= 2);
946 uops = new StaticInstPtr[numMicroops];
947 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
948 _base, _add, _imm);
949 uops[0]->setDelayedCommit();
950 uops[1] = new %(wb_decl)s;
951 uops[1]->setLastMicroop();
952#endif
953 }
954}};
955
956def template LoadStoreImmConstructor {{
957 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
958 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
959 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
960 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
961 {
962 %(constructor)s;
963 if (!(condCode == COND_AL || condCode == COND_UC)) {
964 for (int x = 0; x < _numDestRegs; x++) {
965 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
966 }
967 }
968#if %(use_uops)d
969 assert(numMicroops >= 2);
970 uops = new StaticInstPtr[numMicroops];
971 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
972 uops[0]->setDelayedCommit();
973 uops[1] = new %(wb_decl)s;
974 uops[1]->setLastMicroop();
975#endif
976 }
977}};
978
979def template StoreExImmConstructor {{
980 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
981 uint32_t _result, uint32_t _dest, uint32_t _base,
982 bool _add, int32_t _imm)
983 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
984 (IntRegIndex)_result, (IntRegIndex)_dest,
985 (IntRegIndex)_base, _add, _imm)
986 {
987 %(constructor)s;
988 if (!(condCode == COND_AL || condCode == COND_UC)) {
989 for (int x = 0; x < _numDestRegs; x++) {
990 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
991 }
992 }
993#if %(use_uops)d
994 assert(numMicroops >= 2);
995 uops = new StaticInstPtr[numMicroops];
996 uops[0] = new %(acc_name)s(machInst, _result, _dest,
997 _base, _add, _imm);
998 uops[0]->setDelayedCommit();
999 uops[1] = new %(wb_decl)s;
1000 uops[1]->setLastMicroop();
1001#endif
1002 }
1003}};
1004
1005def template StoreDRegConstructor {{
1006 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1007 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1008 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1009 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1010 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1011 (IntRegIndex)_base, _add,
1012 _shiftAmt, (ArmShiftType)_shiftType,
1013 (IntRegIndex)_index)
1014 {
1015 %(constructor)s;
1016 if (!(condCode == COND_AL || condCode == COND_UC)) {
1017 for (int x = 0; x < _numDestRegs; x++) {
1018 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1019 }
1020 }
1021#if %(use_uops)d
1022 assert(numMicroops >= 2);
1023 uops = new StaticInstPtr[numMicroops];
1024 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1025 _shiftAmt, _shiftType, _index);
1026 uops[0]->setDelayedCommit();
1027 uops[1] = new %(wb_decl)s;
1028 uops[1]->setLastMicroop();
1029#endif
1030 }
1031}};
1032
1033def template StoreRegConstructor {{
1034 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1035 uint32_t _dest, uint32_t _base, bool _add,
1036 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1037 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1038 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1039 _shiftAmt, (ArmShiftType)_shiftType,
1040 (IntRegIndex)_index)
1041 {
1042 %(constructor)s;
1043 if (!(condCode == COND_AL || condCode == COND_UC)) {
1044 for (int x = 0; x < _numDestRegs; x++) {
1045 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1046 }
1047 }
1048#if %(use_uops)d
1049 assert(numMicroops >= 2);
1050 uops = new StaticInstPtr[numMicroops];
1051 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1052 _shiftAmt, _shiftType, _index);
1053 uops[0]->setDelayedCommit();
1054 uops[1] = new %(wb_decl)s;
1055 uops[1]->setLastMicroop();
1056#endif
1057 }
1058}};
1059
1060def template LoadDRegConstructor {{
1061 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1062 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1063 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1064 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1065 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1066 (IntRegIndex)_base, _add,
1067 _shiftAmt, (ArmShiftType)_shiftType,
1068 (IntRegIndex)_index)
1069 {
1070 %(constructor)s;
1071 if (!(condCode == COND_AL || condCode == COND_UC)) {
1072 for (int x = 0; x < _numDestRegs; x++) {
1073 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1074 }
1075 }
1076#if %(use_uops)d
1077 assert(numMicroops >= 2);
1078 uops = new StaticInstPtr[numMicroops];
1079 if ((_dest == _index) || (_dest2 == _index)) {
1080 IntRegIndex wbIndexReg = INTREG_UREG0;
1081 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1082 uops[0]->setDelayedCommit();
1083 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1084 _shiftAmt, _shiftType, _index);
1085 uops[1]->setDelayedCommit();
1086 uops[2] = new %(wb_decl)s;
1087 uops[2]->setLastMicroop();
1088 } else {
1089 IntRegIndex wbIndexReg = index;
1090 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1091 _shiftAmt, _shiftType, _index);
1092 uops[0]->setDelayedCommit();
1093 uops[1] = new %(wb_decl)s;
1094 uops[1]->setLastMicroop();
1095 }
1096#endif
1097 }
1098}};
1099
1100def template LoadRegConstructor {{
1101 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1102 uint32_t _dest, uint32_t _base, bool _add,
1103 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1104 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1105 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1106 _shiftAmt, (ArmShiftType)_shiftType,
1107 (IntRegIndex)_index)
1108 {
1109 %(constructor)s;
1110 bool conditional = false;
1111 if (!(condCode == COND_AL || condCode == COND_UC)) {
1112 conditional = true;
1113 for (int x = 0; x < _numDestRegs; x++) {
1114 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1115 }
1116 }
1117#if %(use_uops)d
1118 assert(numMicroops >= 2);
1119 uops = new StaticInstPtr[numMicroops];
1120 if (_dest == INTREG_PC) {
1121 IntRegIndex wbIndexReg = index;
1122 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1123 _shiftAmt, _shiftType, _index);
1124 uops[0]->setDelayedCommit();
1125 uops[1] = new %(wb_decl)s;
1126 uops[1]->setDelayedCommit();
1127 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1128 uops[2]->setFlag(StaticInst::IsControl);
1129 uops[2]->setFlag(StaticInst::IsIndirectControl);
1130 if (conditional)
1131 uops[2]->setFlag(StaticInst::IsCondControl);
1132 else
1133 uops[2]->setFlag(StaticInst::IsUncondControl);
1134 uops[2]->setLastMicroop();
1135 } else if(_dest == _index) {
1136 IntRegIndex wbIndexReg = INTREG_UREG0;
1137 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1138 uops[0]->setDelayedCommit();
1139 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1140 _shiftAmt, _shiftType, _index);
1141 uops[1]->setDelayedCommit();
1142 uops[2] = new %(wb_decl)s;
1143 uops[2]->setLastMicroop();
1144 } else {
1145 IntRegIndex wbIndexReg = index;
1146 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1147 _shiftAmt, _shiftType, _index);
1148 uops[0]->setDelayedCommit();
1149 uops[1] = new %(wb_decl)s;
1150 uops[1]->setLastMicroop();
1151
1152 }
1153#endif
1154 }
1155}};
1156
1157def template LoadImmConstructor {{
1158 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1159 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1160 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1161 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1162 {
1163 %(constructor)s;
1164 bool conditional = false;
1165 if (!(condCode == COND_AL || condCode == COND_UC)) {
1166 conditional = true;
1167 for (int x = 0; x < _numDestRegs; x++) {
1168 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1169 }
1170 }
1171#if %(use_uops)d
1172 assert(numMicroops >= 2);
1173 uops = new StaticInstPtr[numMicroops];
1174 if (_dest == INTREG_PC) {
1175 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1176 _imm);
1177 uops[0]->setDelayedCommit();
1178 uops[1] = new %(wb_decl)s;
1179 uops[1]->setDelayedCommit();
1180 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1181 uops[2]->setFlag(StaticInst::IsControl);
1182 uops[2]->setFlag(StaticInst::IsIndirectControl);
1183 if (conditional)
1184 uops[2]->setFlag(StaticInst::IsCondControl);
1185 else
1186 uops[2]->setFlag(StaticInst::IsUncondControl);
1187 if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
1188 uops[2]->setFlag(StaticInst::IsReturn);
1189 uops[2]->setLastMicroop();
1190 } else {
1191 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1192 uops[0]->setDelayedCommit();
1193 uops[1] = new %(wb_decl)s;
1194 uops[1]->setLastMicroop();
1195 }
1196#endif
1197 }
1198}};
1199