521 }
522
523 return fault;
524 }
525}};
526
527def template LoadCompleteAcc {{
528 Fault %(class_name)s::completeAcc(PacketPtr pkt,
529 %(CPU_exec_context)s *xc,
530 Trace::InstRecord *traceData) const
531 {
532 Fault fault = NoFault;
533
534 %(op_decl)s;
535 %(op_rd)s;
536
537 if (%(predicate_test)s)
538 {
539 // ARM instructions will not have a pkt if the predicate is false
540 Mem = pkt->get<typeof(Mem)>();
541
542 if (fault == NoFault) {
543 %(memacc_code)s;
544 }
545
546 if (fault == NoFault) {
547 %(op_wb)s;
548 }
549 }
550
551 if (fault == NoFault && machInst.itstateMask != 0) {
552 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
553 }
554
555 return fault;
556 }
557}};
558
559def template NeonLoadCompleteAcc {{
560 template <class Element>
561 Fault %(class_name)s<Element>::completeAcc(
562 PacketPtr pkt, %(CPU_exec_context)s *xc,
563 Trace::InstRecord *traceData) const
564 {
565 Fault fault = NoFault;
566
567 %(mem_decl)s;
568 %(op_decl)s;
569 %(op_rd)s;
570
571 if (%(predicate_test)s)
572 {
573 // ARM instructions will not have a pkt if the predicate is false
574 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
575
576 if (fault == NoFault) {
577 %(memacc_code)s;
578 }
579
580 if (fault == NoFault) {
581 %(op_wb)s;
582 }
583 }
584
585 if (fault == NoFault && machInst.itstateMask != 0) {
586 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
587 }
588
589 return fault;
590 }
591}};
592
593def template StoreCompleteAcc {{
594 Fault %(class_name)s::completeAcc(PacketPtr pkt,
595 %(CPU_exec_context)s *xc,
596 Trace::InstRecord *traceData) const
597 {
598 if (machInst.itstateMask != 0) {
599 warn_once("Complete acc isn't called on normal stores in O3.");
600 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
601 }
602 return NoFault;
603 }
604}};
605
606def template NeonStoreCompleteAcc {{
607 template <class Element>
608 Fault %(class_name)s<Element>::completeAcc(
609 PacketPtr pkt, %(CPU_exec_context)s *xc,
610 Trace::InstRecord *traceData) const
611 {
612 if (machInst.itstateMask != 0) {
613 warn_once("Complete acc isn't called on normal stores in O3.");
614 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
615 }
616 return NoFault;
617 }
618}};
619
620def template StoreExCompleteAcc {{
621 Fault %(class_name)s::completeAcc(PacketPtr pkt,
622 %(CPU_exec_context)s *xc,
623 Trace::InstRecord *traceData) const
624 {
625 Fault fault = NoFault;
626
627 %(op_decl)s;
628 %(op_rd)s;
629
630 if (%(predicate_test)s)
631 {
632 uint64_t writeResult = pkt->req->getExtraData();
633 %(postacc_code)s;
634
635 if (fault == NoFault) {
636 %(op_wb)s;
637 }
638 }
639
640 if (fault == NoFault && machInst.itstateMask != 0) {
641 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
642 }
643
644 return fault;
645 }
646}};
647
648def template RfeDeclare {{
649 /**
650 * Static instruction class for "%(mnemonic)s".
651 */
652 class %(class_name)s : public %(base_class)s
653 {
654 public:
655
656 /// Constructor.
657 %(class_name)s(ExtMachInst machInst,
658 uint32_t _base, int _mode, bool _wb);
659
660 %(BasicExecDeclare)s
661
662 %(InitiateAccDeclare)s
663
664 %(CompleteAccDeclare)s
665 };
666}};
667
668def template SrsDeclare {{
669 /**
670 * Static instruction class for "%(mnemonic)s".
671 */
672 class %(class_name)s : public %(base_class)s
673 {
674 public:
675
676 /// Constructor.
677 %(class_name)s(ExtMachInst machInst,
678 uint32_t _regMode, int _mode, bool _wb);
679
680 %(BasicExecDeclare)s
681
682 %(InitiateAccDeclare)s
683
684 %(CompleteAccDeclare)s
685 };
686}};
687
688def template SwapDeclare {{
689 /**
690 * Static instruction class for "%(mnemonic)s".
691 */
692 class %(class_name)s : public %(base_class)s
693 {
694 public:
695
696 /// Constructor.
697 %(class_name)s(ExtMachInst machInst,
698 uint32_t _dest, uint32_t _op1, uint32_t _base);
699
700 %(BasicExecDeclare)s
701
702 %(InitiateAccDeclare)s
703
704 %(CompleteAccDeclare)s
705 };
706}};
707
708def template LoadStoreDImmDeclare {{
709 /**
710 * Static instruction class for "%(mnemonic)s".
711 */
712 class %(class_name)s : public %(base_class)s
713 {
714 public:
715
716 /// Constructor.
717 %(class_name)s(ExtMachInst machInst,
718 uint32_t _dest, uint32_t _dest2,
719 uint32_t _base, bool _add, int32_t _imm);
720
721 %(BasicExecDeclare)s
722
723 %(InitiateAccDeclare)s
724
725 %(CompleteAccDeclare)s
726 };
727}};
728
729def template StoreExDImmDeclare {{
730 /**
731 * Static instruction class for "%(mnemonic)s".
732 */
733 class %(class_name)s : public %(base_class)s
734 {
735 public:
736
737 /// Constructor.
738 %(class_name)s(ExtMachInst machInst,
739 uint32_t _result, uint32_t _dest, uint32_t _dest2,
740 uint32_t _base, bool _add, int32_t _imm);
741
742 %(BasicExecDeclare)s
743
744 %(InitiateAccDeclare)s
745
746 %(CompleteAccDeclare)s
747 };
748}};
749
750def template LoadStoreImmDeclare {{
751 /**
752 * Static instruction class for "%(mnemonic)s".
753 */
754 class %(class_name)s : public %(base_class)s
755 {
756 public:
757
758 /// Constructor.
759 %(class_name)s(ExtMachInst machInst,
760 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
761
762 %(BasicExecDeclare)s
763
764 %(InitiateAccDeclare)s
765
766 %(CompleteAccDeclare)s
767 };
768}};
769
770def template StoreExImmDeclare {{
771 /**
772 * Static instruction class for "%(mnemonic)s".
773 */
774 class %(class_name)s : public %(base_class)s
775 {
776 public:
777
778 /// Constructor.
779 %(class_name)s(ExtMachInst machInst,
780 uint32_t _result, uint32_t _dest, uint32_t _base,
781 bool _add, int32_t _imm);
782
783 %(BasicExecDeclare)s
784
785 %(InitiateAccDeclare)s
786
787 %(CompleteAccDeclare)s
788 };
789}};
790
791def template StoreDRegDeclare {{
792 /**
793 * Static instruction class for "%(mnemonic)s".
794 */
795 class %(class_name)s : public %(base_class)s
796 {
797 public:
798
799 /// Constructor.
800 %(class_name)s(ExtMachInst machInst,
801 uint32_t _dest, uint32_t _dest2,
802 uint32_t _base, bool _add,
803 int32_t _shiftAmt, uint32_t _shiftType,
804 uint32_t _index);
805
806 %(BasicExecDeclare)s
807
808 %(InitiateAccDeclare)s
809
810 %(CompleteAccDeclare)s
811 };
812}};
813
814def template StoreRegDeclare {{
815 /**
816 * Static instruction class for "%(mnemonic)s".
817 */
818 class %(class_name)s : public %(base_class)s
819 {
820 public:
821
822 /// Constructor.
823 %(class_name)s(ExtMachInst machInst,
824 uint32_t _dest, uint32_t _base, bool _add,
825 int32_t _shiftAmt, uint32_t _shiftType,
826 uint32_t _index);
827
828 %(BasicExecDeclare)s
829
830 %(InitiateAccDeclare)s
831
832 %(CompleteAccDeclare)s
833 };
834}};
835
836def template LoadDRegDeclare {{
837 /**
838 * Static instruction class for "%(mnemonic)s".
839 */
840 class %(class_name)s : public %(base_class)s
841 {
842 public:
843
844 /// Constructor.
845 %(class_name)s(ExtMachInst machInst,
846 uint32_t _dest, uint32_t _dest2,
847 uint32_t _base, bool _add,
848 int32_t _shiftAmt, uint32_t _shiftType,
849 uint32_t _index);
850
851 %(BasicExecDeclare)s
852
853 %(InitiateAccDeclare)s
854
855 %(CompleteAccDeclare)s
856 };
857}};
858
859def template LoadRegDeclare {{
860 /**
861 * Static instruction class for "%(mnemonic)s".
862 */
863 class %(class_name)s : public %(base_class)s
864 {
865 public:
866
867 /// Constructor.
868 %(class_name)s(ExtMachInst machInst,
869 uint32_t _dest, uint32_t _base, bool _add,
870 int32_t _shiftAmt, uint32_t _shiftType,
871 uint32_t _index);
872
873 %(BasicExecDeclare)s
874
875 %(InitiateAccDeclare)s
876
877 %(CompleteAccDeclare)s
878 };
879}};
880
881def template LoadImmDeclare {{
882 /**
883 * Static instruction class for "%(mnemonic)s".
884 */
885 class %(class_name)s : public %(base_class)s
886 {
887 public:
888
889 /// Constructor.
890 %(class_name)s(ExtMachInst machInst,
891 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
892
893 %(BasicExecDeclare)s
894
895 %(InitiateAccDeclare)s
896
897 %(CompleteAccDeclare)s
898 };
899}};
900
901def template InitiateAccDeclare {{
902 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
903}};
904
905def template CompleteAccDeclare {{
906 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
907}};
908
909def template RfeConstructor {{
910 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
911 uint32_t _base, int _mode, bool _wb)
912 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
913 (IntRegIndex)_base, (AddrMode)_mode, _wb)
914 {
915 %(constructor)s;
916 if (!(condCode == COND_AL || condCode == COND_UC)) {
917 for (int x = 0; x < _numDestRegs; x++) {
918 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
919 }
920 }
921#if %(use_uops)d
922 assert(numMicroops >= 2);
923 uops = new StaticInstPtr[numMicroops];
924 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
925 uops[0]->setDelayedCommit();
926 uops[1] = new %(wb_decl)s;
927 uops[1]->setLastMicroop();
928#endif
929 }
930}};
931
932def template SrsConstructor {{
933 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
934 uint32_t _regMode, int _mode, bool _wb)
935 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
936 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
937 {
938 %(constructor)s;
939 if (!(condCode == COND_AL || condCode == COND_UC)) {
940 for (int x = 0; x < _numDestRegs; x++) {
941 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
942 }
943 }
944#if %(use_uops)d
945 assert(numMicroops >= 2);
946 uops = new StaticInstPtr[numMicroops];
947 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
948 uops[0]->setDelayedCommit();
949 uops[1] = new %(wb_decl)s;
950 uops[1]->setLastMicroop();
951#endif
952 }
953}};
954
955def template SwapConstructor {{
956 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
957 uint32_t _dest, uint32_t _op1, uint32_t _base)
958 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
959 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
960 {
961 %(constructor)s;
962 if (!(condCode == COND_AL || condCode == COND_UC)) {
963 for (int x = 0; x < _numDestRegs; x++) {
964 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
965 }
966 }
967 }
968}};
969
970def template LoadStoreDImmConstructor {{
971 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
972 uint32_t _dest, uint32_t _dest2,
973 uint32_t _base, bool _add, int32_t _imm)
974 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
975 (IntRegIndex)_dest, (IntRegIndex)_dest2,
976 (IntRegIndex)_base, _add, _imm)
977 {
978 %(constructor)s;
979 if (!(condCode == COND_AL || condCode == COND_UC)) {
980 for (int x = 0; x < _numDestRegs; x++) {
981 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
982 }
983 }
984#if %(use_uops)d
985 assert(numMicroops >= 2);
986 uops = new StaticInstPtr[numMicroops];
987 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
988 uops[0]->setDelayedCommit();
989 uops[1] = new %(wb_decl)s;
990 uops[1]->setLastMicroop();
991#endif
992 }
993}};
994
995def template StoreExDImmConstructor {{
996 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
997 uint32_t _result, uint32_t _dest, uint32_t _dest2,
998 uint32_t _base, bool _add, int32_t _imm)
999 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1000 (IntRegIndex)_result,
1001 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1002 (IntRegIndex)_base, _add, _imm)
1003 {
1004 %(constructor)s;
1005 if (!(condCode == COND_AL || condCode == COND_UC)) {
1006 for (int x = 0; x < _numDestRegs; x++) {
1007 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1008 }
1009 }
1010#if %(use_uops)d
1011 assert(numMicroops >= 2);
1012 uops = new StaticInstPtr[numMicroops];
1013 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
1014 _base, _add, _imm);
1015 uops[0]->setDelayedCommit();
1016 uops[1] = new %(wb_decl)s;
1017 uops[1]->setLastMicroop();
1018#endif
1019 }
1020}};
1021
1022def template LoadStoreImmConstructor {{
1023 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1024 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1025 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1026 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1027 {
1028 %(constructor)s;
1029 if (!(condCode == COND_AL || condCode == COND_UC)) {
1030 for (int x = 0; x < _numDestRegs; x++) {
1031 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1032 }
1033 }
1034#if %(use_uops)d
1035 assert(numMicroops >= 2);
1036 uops = new StaticInstPtr[numMicroops];
1037 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1038 uops[0]->setDelayedCommit();
1039 uops[1] = new %(wb_decl)s;
1040 uops[1]->setLastMicroop();
1041#endif
1042 }
1043}};
1044
1045def template StoreExImmConstructor {{
1046 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1047 uint32_t _result, uint32_t _dest, uint32_t _base,
1048 bool _add, int32_t _imm)
1049 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1050 (IntRegIndex)_result, (IntRegIndex)_dest,
1051 (IntRegIndex)_base, _add, _imm)
1052 {
1053 %(constructor)s;
1054 if (!(condCode == COND_AL || condCode == COND_UC)) {
1055 for (int x = 0; x < _numDestRegs; x++) {
1056 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1057 }
1058 }
1059#if %(use_uops)d
1060 assert(numMicroops >= 2);
1061 uops = new StaticInstPtr[numMicroops];
1062 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1063 _base, _add, _imm);
1064 uops[0]->setDelayedCommit();
1065 uops[1] = new %(wb_decl)s;
1066 uops[1]->setLastMicroop();
1067#endif
1068 }
1069}};
1070
1071def template StoreDRegConstructor {{
1072 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1073 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1074 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1075 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1076 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1077 (IntRegIndex)_base, _add,
1078 _shiftAmt, (ArmShiftType)_shiftType,
1079 (IntRegIndex)_index)
1080 {
1081 %(constructor)s;
1082 if (!(condCode == COND_AL || condCode == COND_UC)) {
1083 for (int x = 0; x < _numDestRegs; x++) {
1084 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1085 }
1086 }
1087#if %(use_uops)d
1088 assert(numMicroops >= 2);
1089 uops = new StaticInstPtr[numMicroops];
1090 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1091 _shiftAmt, _shiftType, _index);
1092 uops[0]->setDelayedCommit();
1093 uops[1] = new %(wb_decl)s;
1094 uops[1]->setLastMicroop();
1095#endif
1096 }
1097}};
1098
1099def template StoreRegConstructor {{
1100 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1101 uint32_t _dest, uint32_t _base, bool _add,
1102 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1103 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1104 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1105 _shiftAmt, (ArmShiftType)_shiftType,
1106 (IntRegIndex)_index)
1107 {
1108 %(constructor)s;
1109 if (!(condCode == COND_AL || condCode == COND_UC)) {
1110 for (int x = 0; x < _numDestRegs; x++) {
1111 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1112 }
1113 }
1114#if %(use_uops)d
1115 assert(numMicroops >= 2);
1116 uops = new StaticInstPtr[numMicroops];
1117 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1118 _shiftAmt, _shiftType, _index);
1119 uops[0]->setDelayedCommit();
1120 uops[1] = new %(wb_decl)s;
1121 uops[1]->setLastMicroop();
1122#endif
1123 }
1124}};
1125
1126def template LoadDRegConstructor {{
1127 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1128 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1129 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1131 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1132 (IntRegIndex)_base, _add,
1133 _shiftAmt, (ArmShiftType)_shiftType,
1134 (IntRegIndex)_index)
1135 {
1136 %(constructor)s;
1137 if (!(condCode == COND_AL || condCode == COND_UC)) {
1138 for (int x = 0; x < _numDestRegs; x++) {
1139 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1140 }
1141 }
1142#if %(use_uops)d
1143 assert(numMicroops >= 2);
1144 uops = new StaticInstPtr[numMicroops];
1145 if ((_dest == _index) || (_dest2 == _index)) {
1146 IntRegIndex wbIndexReg = INTREG_UREG0;
1147 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1148 uops[0]->setDelayedCommit();
1149 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1150 _shiftAmt, _shiftType, _index);
1151 uops[1]->setDelayedCommit();
1152 uops[2] = new %(wb_decl)s;
1153 uops[2]->setLastMicroop();
1154 } else {
1155 IntRegIndex wbIndexReg = index;
1156 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1157 _shiftAmt, _shiftType, _index);
1158 uops[0]->setDelayedCommit();
1159 uops[1] = new %(wb_decl)s;
1160 uops[1]->setLastMicroop();
1161 }
1162#endif
1163 }
1164}};
1165
1166def template LoadRegConstructor {{
1167 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1168 uint32_t _dest, uint32_t _base, bool _add,
1169 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1170 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1171 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1172 _shiftAmt, (ArmShiftType)_shiftType,
1173 (IntRegIndex)_index)
1174 {
1175 %(constructor)s;
1176 if (!(condCode == COND_AL || condCode == COND_UC)) {
1177 for (int x = 0; x < _numDestRegs; x++) {
1178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1179 }
1180 }
1181#if %(use_uops)d
1182 assert(numMicroops >= 2);
1183 uops = new StaticInstPtr[numMicroops];
1184 if (_dest == INTREG_PC) {
1185 IntRegIndex wbIndexReg = index;
1186 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1187 _shiftAmt, _shiftType, _index);
1188 uops[0]->setDelayedCommit();
1189 uops[1] = new %(wb_decl)s;
1190 uops[1]->setDelayedCommit();
1191 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1192 uops[2]->setLastMicroop();
1193 } else if(_dest == _index) {
1194 IntRegIndex wbIndexReg = INTREG_UREG0;
1195 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1196 uops[0]->setDelayedCommit();
1197 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1198 _shiftAmt, _shiftType, _index);
1199 uops[1]->setDelayedCommit();
1200 uops[2] = new %(wb_decl)s;
1201 uops[2]->setLastMicroop();
1202 } else {
1203 IntRegIndex wbIndexReg = index;
1204 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1205 _shiftAmt, _shiftType, _index);
1206 uops[0]->setDelayedCommit();
1207 uops[1] = new %(wb_decl)s;
1208 uops[1]->setLastMicroop();
1209
1210 }
1211#endif
1212 }
1213}};
1214
1215def template LoadImmConstructor {{
1216 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1217 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1218 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1219 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1220 {
1221 %(constructor)s;
1222 if (!(condCode == COND_AL || condCode == COND_UC)) {
1223 for (int x = 0; x < _numDestRegs; x++) {
1224 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1225 }
1226 }
1227#if %(use_uops)d
1228 assert(numMicroops >= 2);
1229 uops = new StaticInstPtr[numMicroops];
1230 if (_dest == INTREG_PC) {
1231 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1232 _imm);
1233 uops[0]->setDelayedCommit();
1234 uops[1] = new %(wb_decl)s;
1235 uops[1]->setDelayedCommit();
1236 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1237 uops[2]->setLastMicroop();
1238 } else {
1239 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1240 uops[0]->setDelayedCommit();
1241 uops[1] = new %(wb_decl)s;
1242 uops[1]->setLastMicroop();
1243 }
1244#endif
1245 }
1246}};
1247
| 530 }
531
532 return fault;
533 }
534}};
535
536def template LoadCompleteAcc {{
537 Fault %(class_name)s::completeAcc(PacketPtr pkt,
538 %(CPU_exec_context)s *xc,
539 Trace::InstRecord *traceData) const
540 {
541 Fault fault = NoFault;
542
543 %(op_decl)s;
544 %(op_rd)s;
545
546 if (%(predicate_test)s)
547 {
548 // ARM instructions will not have a pkt if the predicate is false
549 Mem = pkt->get<typeof(Mem)>();
550
551 if (fault == NoFault) {
552 %(memacc_code)s;
553 }
554
555 if (fault == NoFault) {
556 %(op_wb)s;
557 }
558 }
559
560 if (fault == NoFault && machInst.itstateMask != 0) {
561 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
562 }
563
564 return fault;
565 }
566}};
567
568def template NeonLoadCompleteAcc {{
569 template <class Element>
570 Fault %(class_name)s<Element>::completeAcc(
571 PacketPtr pkt, %(CPU_exec_context)s *xc,
572 Trace::InstRecord *traceData) const
573 {
574 Fault fault = NoFault;
575
576 %(mem_decl)s;
577 %(op_decl)s;
578 %(op_rd)s;
579
580 if (%(predicate_test)s)
581 {
582 // ARM instructions will not have a pkt if the predicate is false
583 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
584
585 if (fault == NoFault) {
586 %(memacc_code)s;
587 }
588
589 if (fault == NoFault) {
590 %(op_wb)s;
591 }
592 }
593
594 if (fault == NoFault && machInst.itstateMask != 0) {
595 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
596 }
597
598 return fault;
599 }
600}};
601
602def template StoreCompleteAcc {{
603 Fault %(class_name)s::completeAcc(PacketPtr pkt,
604 %(CPU_exec_context)s *xc,
605 Trace::InstRecord *traceData) const
606 {
607 if (machInst.itstateMask != 0) {
608 warn_once("Complete acc isn't called on normal stores in O3.");
609 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
610 }
611 return NoFault;
612 }
613}};
614
615def template NeonStoreCompleteAcc {{
616 template <class Element>
617 Fault %(class_name)s<Element>::completeAcc(
618 PacketPtr pkt, %(CPU_exec_context)s *xc,
619 Trace::InstRecord *traceData) const
620 {
621 if (machInst.itstateMask != 0) {
622 warn_once("Complete acc isn't called on normal stores in O3.");
623 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
624 }
625 return NoFault;
626 }
627}};
628
629def template StoreExCompleteAcc {{
630 Fault %(class_name)s::completeAcc(PacketPtr pkt,
631 %(CPU_exec_context)s *xc,
632 Trace::InstRecord *traceData) const
633 {
634 Fault fault = NoFault;
635
636 %(op_decl)s;
637 %(op_rd)s;
638
639 if (%(predicate_test)s)
640 {
641 uint64_t writeResult = pkt->req->getExtraData();
642 %(postacc_code)s;
643
644 if (fault == NoFault) {
645 %(op_wb)s;
646 }
647 }
648
649 if (fault == NoFault && machInst.itstateMask != 0) {
650 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
651 }
652
653 return fault;
654 }
655}};
656
657def template RfeDeclare {{
658 /**
659 * Static instruction class for "%(mnemonic)s".
660 */
661 class %(class_name)s : public %(base_class)s
662 {
663 public:
664
665 /// Constructor.
666 %(class_name)s(ExtMachInst machInst,
667 uint32_t _base, int _mode, bool _wb);
668
669 %(BasicExecDeclare)s
670
671 %(InitiateAccDeclare)s
672
673 %(CompleteAccDeclare)s
674 };
675}};
676
677def template SrsDeclare {{
678 /**
679 * Static instruction class for "%(mnemonic)s".
680 */
681 class %(class_name)s : public %(base_class)s
682 {
683 public:
684
685 /// Constructor.
686 %(class_name)s(ExtMachInst machInst,
687 uint32_t _regMode, int _mode, bool _wb);
688
689 %(BasicExecDeclare)s
690
691 %(InitiateAccDeclare)s
692
693 %(CompleteAccDeclare)s
694 };
695}};
696
697def template SwapDeclare {{
698 /**
699 * Static instruction class for "%(mnemonic)s".
700 */
701 class %(class_name)s : public %(base_class)s
702 {
703 public:
704
705 /// Constructor.
706 %(class_name)s(ExtMachInst machInst,
707 uint32_t _dest, uint32_t _op1, uint32_t _base);
708
709 %(BasicExecDeclare)s
710
711 %(InitiateAccDeclare)s
712
713 %(CompleteAccDeclare)s
714 };
715}};
716
717def template LoadStoreDImmDeclare {{
718 /**
719 * Static instruction class for "%(mnemonic)s".
720 */
721 class %(class_name)s : public %(base_class)s
722 {
723 public:
724
725 /// Constructor.
726 %(class_name)s(ExtMachInst machInst,
727 uint32_t _dest, uint32_t _dest2,
728 uint32_t _base, bool _add, int32_t _imm);
729
730 %(BasicExecDeclare)s
731
732 %(InitiateAccDeclare)s
733
734 %(CompleteAccDeclare)s
735 };
736}};
737
738def template StoreExDImmDeclare {{
739 /**
740 * Static instruction class for "%(mnemonic)s".
741 */
742 class %(class_name)s : public %(base_class)s
743 {
744 public:
745
746 /// Constructor.
747 %(class_name)s(ExtMachInst machInst,
748 uint32_t _result, uint32_t _dest, uint32_t _dest2,
749 uint32_t _base, bool _add, int32_t _imm);
750
751 %(BasicExecDeclare)s
752
753 %(InitiateAccDeclare)s
754
755 %(CompleteAccDeclare)s
756 };
757}};
758
759def template LoadStoreImmDeclare {{
760 /**
761 * Static instruction class for "%(mnemonic)s".
762 */
763 class %(class_name)s : public %(base_class)s
764 {
765 public:
766
767 /// Constructor.
768 %(class_name)s(ExtMachInst machInst,
769 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
770
771 %(BasicExecDeclare)s
772
773 %(InitiateAccDeclare)s
774
775 %(CompleteAccDeclare)s
776 };
777}};
778
779def template StoreExImmDeclare {{
780 /**
781 * Static instruction class for "%(mnemonic)s".
782 */
783 class %(class_name)s : public %(base_class)s
784 {
785 public:
786
787 /// Constructor.
788 %(class_name)s(ExtMachInst machInst,
789 uint32_t _result, uint32_t _dest, uint32_t _base,
790 bool _add, int32_t _imm);
791
792 %(BasicExecDeclare)s
793
794 %(InitiateAccDeclare)s
795
796 %(CompleteAccDeclare)s
797 };
798}};
799
800def template StoreDRegDeclare {{
801 /**
802 * Static instruction class for "%(mnemonic)s".
803 */
804 class %(class_name)s : public %(base_class)s
805 {
806 public:
807
808 /// Constructor.
809 %(class_name)s(ExtMachInst machInst,
810 uint32_t _dest, uint32_t _dest2,
811 uint32_t _base, bool _add,
812 int32_t _shiftAmt, uint32_t _shiftType,
813 uint32_t _index);
814
815 %(BasicExecDeclare)s
816
817 %(InitiateAccDeclare)s
818
819 %(CompleteAccDeclare)s
820 };
821}};
822
823def template StoreRegDeclare {{
824 /**
825 * Static instruction class for "%(mnemonic)s".
826 */
827 class %(class_name)s : public %(base_class)s
828 {
829 public:
830
831 /// Constructor.
832 %(class_name)s(ExtMachInst machInst,
833 uint32_t _dest, uint32_t _base, bool _add,
834 int32_t _shiftAmt, uint32_t _shiftType,
835 uint32_t _index);
836
837 %(BasicExecDeclare)s
838
839 %(InitiateAccDeclare)s
840
841 %(CompleteAccDeclare)s
842 };
843}};
844
845def template LoadDRegDeclare {{
846 /**
847 * Static instruction class for "%(mnemonic)s".
848 */
849 class %(class_name)s : public %(base_class)s
850 {
851 public:
852
853 /// Constructor.
854 %(class_name)s(ExtMachInst machInst,
855 uint32_t _dest, uint32_t _dest2,
856 uint32_t _base, bool _add,
857 int32_t _shiftAmt, uint32_t _shiftType,
858 uint32_t _index);
859
860 %(BasicExecDeclare)s
861
862 %(InitiateAccDeclare)s
863
864 %(CompleteAccDeclare)s
865 };
866}};
867
868def template LoadRegDeclare {{
869 /**
870 * Static instruction class for "%(mnemonic)s".
871 */
872 class %(class_name)s : public %(base_class)s
873 {
874 public:
875
876 /// Constructor.
877 %(class_name)s(ExtMachInst machInst,
878 uint32_t _dest, uint32_t _base, bool _add,
879 int32_t _shiftAmt, uint32_t _shiftType,
880 uint32_t _index);
881
882 %(BasicExecDeclare)s
883
884 %(InitiateAccDeclare)s
885
886 %(CompleteAccDeclare)s
887 };
888}};
889
890def template LoadImmDeclare {{
891 /**
892 * Static instruction class for "%(mnemonic)s".
893 */
894 class %(class_name)s : public %(base_class)s
895 {
896 public:
897
898 /// Constructor.
899 %(class_name)s(ExtMachInst machInst,
900 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
901
902 %(BasicExecDeclare)s
903
904 %(InitiateAccDeclare)s
905
906 %(CompleteAccDeclare)s
907 };
908}};
909
910def template InitiateAccDeclare {{
911 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
912}};
913
914def template CompleteAccDeclare {{
915 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
916}};
917
918def template RfeConstructor {{
919 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
920 uint32_t _base, int _mode, bool _wb)
921 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
922 (IntRegIndex)_base, (AddrMode)_mode, _wb)
923 {
924 %(constructor)s;
925 if (!(condCode == COND_AL || condCode == COND_UC)) {
926 for (int x = 0; x < _numDestRegs; x++) {
927 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
928 }
929 }
930#if %(use_uops)d
931 assert(numMicroops >= 2);
932 uops = new StaticInstPtr[numMicroops];
933 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
934 uops[0]->setDelayedCommit();
935 uops[1] = new %(wb_decl)s;
936 uops[1]->setLastMicroop();
937#endif
938 }
939}};
940
941def template SrsConstructor {{
942 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
943 uint32_t _regMode, int _mode, bool _wb)
944 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
945 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
946 {
947 %(constructor)s;
948 if (!(condCode == COND_AL || condCode == COND_UC)) {
949 for (int x = 0; x < _numDestRegs; x++) {
950 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
951 }
952 }
953#if %(use_uops)d
954 assert(numMicroops >= 2);
955 uops = new StaticInstPtr[numMicroops];
956 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
957 uops[0]->setDelayedCommit();
958 uops[1] = new %(wb_decl)s;
959 uops[1]->setLastMicroop();
960#endif
961 }
962}};
963
964def template SwapConstructor {{
965 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
966 uint32_t _dest, uint32_t _op1, uint32_t _base)
967 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
968 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
969 {
970 %(constructor)s;
971 if (!(condCode == COND_AL || condCode == COND_UC)) {
972 for (int x = 0; x < _numDestRegs; x++) {
973 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
974 }
975 }
976 }
977}};
978
979def template LoadStoreDImmConstructor {{
980 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
981 uint32_t _dest, uint32_t _dest2,
982 uint32_t _base, bool _add, int32_t _imm)
983 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
984 (IntRegIndex)_dest, (IntRegIndex)_dest2,
985 (IntRegIndex)_base, _add, _imm)
986 {
987 %(constructor)s;
988 if (!(condCode == COND_AL || condCode == COND_UC)) {
989 for (int x = 0; x < _numDestRegs; x++) {
990 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
991 }
992 }
993#if %(use_uops)d
994 assert(numMicroops >= 2);
995 uops = new StaticInstPtr[numMicroops];
996 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
997 uops[0]->setDelayedCommit();
998 uops[1] = new %(wb_decl)s;
999 uops[1]->setLastMicroop();
1000#endif
1001 }
1002}};
1003
1004def template StoreExDImmConstructor {{
1005 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1006 uint32_t _result, uint32_t _dest, uint32_t _dest2,
1007 uint32_t _base, bool _add, int32_t _imm)
1008 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1009 (IntRegIndex)_result,
1010 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1011 (IntRegIndex)_base, _add, _imm)
1012 {
1013 %(constructor)s;
1014 if (!(condCode == COND_AL || condCode == COND_UC)) {
1015 for (int x = 0; x < _numDestRegs; x++) {
1016 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1017 }
1018 }
1019#if %(use_uops)d
1020 assert(numMicroops >= 2);
1021 uops = new StaticInstPtr[numMicroops];
1022 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
1023 _base, _add, _imm);
1024 uops[0]->setDelayedCommit();
1025 uops[1] = new %(wb_decl)s;
1026 uops[1]->setLastMicroop();
1027#endif
1028 }
1029}};
1030
1031def template LoadStoreImmConstructor {{
1032 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1033 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1034 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1035 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1036 {
1037 %(constructor)s;
1038 if (!(condCode == COND_AL || condCode == COND_UC)) {
1039 for (int x = 0; x < _numDestRegs; x++) {
1040 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1041 }
1042 }
1043#if %(use_uops)d
1044 assert(numMicroops >= 2);
1045 uops = new StaticInstPtr[numMicroops];
1046 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1047 uops[0]->setDelayedCommit();
1048 uops[1] = new %(wb_decl)s;
1049 uops[1]->setLastMicroop();
1050#endif
1051 }
1052}};
1053
1054def template StoreExImmConstructor {{
1055 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1056 uint32_t _result, uint32_t _dest, uint32_t _base,
1057 bool _add, int32_t _imm)
1058 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1059 (IntRegIndex)_result, (IntRegIndex)_dest,
1060 (IntRegIndex)_base, _add, _imm)
1061 {
1062 %(constructor)s;
1063 if (!(condCode == COND_AL || condCode == COND_UC)) {
1064 for (int x = 0; x < _numDestRegs; x++) {
1065 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1066 }
1067 }
1068#if %(use_uops)d
1069 assert(numMicroops >= 2);
1070 uops = new StaticInstPtr[numMicroops];
1071 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1072 _base, _add, _imm);
1073 uops[0]->setDelayedCommit();
1074 uops[1] = new %(wb_decl)s;
1075 uops[1]->setLastMicroop();
1076#endif
1077 }
1078}};
1079
1080def template StoreDRegConstructor {{
1081 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1082 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1083 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1084 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1085 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1086 (IntRegIndex)_base, _add,
1087 _shiftAmt, (ArmShiftType)_shiftType,
1088 (IntRegIndex)_index)
1089 {
1090 %(constructor)s;
1091 if (!(condCode == COND_AL || condCode == COND_UC)) {
1092 for (int x = 0; x < _numDestRegs; x++) {
1093 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1094 }
1095 }
1096#if %(use_uops)d
1097 assert(numMicroops >= 2);
1098 uops = new StaticInstPtr[numMicroops];
1099 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1100 _shiftAmt, _shiftType, _index);
1101 uops[0]->setDelayedCommit();
1102 uops[1] = new %(wb_decl)s;
1103 uops[1]->setLastMicroop();
1104#endif
1105 }
1106}};
1107
1108def template StoreRegConstructor {{
1109 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1110 uint32_t _dest, uint32_t _base, bool _add,
1111 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1112 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1113 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1114 _shiftAmt, (ArmShiftType)_shiftType,
1115 (IntRegIndex)_index)
1116 {
1117 %(constructor)s;
1118 if (!(condCode == COND_AL || condCode == COND_UC)) {
1119 for (int x = 0; x < _numDestRegs; x++) {
1120 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1121 }
1122 }
1123#if %(use_uops)d
1124 assert(numMicroops >= 2);
1125 uops = new StaticInstPtr[numMicroops];
1126 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1127 _shiftAmt, _shiftType, _index);
1128 uops[0]->setDelayedCommit();
1129 uops[1] = new %(wb_decl)s;
1130 uops[1]->setLastMicroop();
1131#endif
1132 }
1133}};
1134
1135def template LoadDRegConstructor {{
1136 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1137 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1138 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1139 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1140 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1141 (IntRegIndex)_base, _add,
1142 _shiftAmt, (ArmShiftType)_shiftType,
1143 (IntRegIndex)_index)
1144 {
1145 %(constructor)s;
1146 if (!(condCode == COND_AL || condCode == COND_UC)) {
1147 for (int x = 0; x < _numDestRegs; x++) {
1148 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1149 }
1150 }
1151#if %(use_uops)d
1152 assert(numMicroops >= 2);
1153 uops = new StaticInstPtr[numMicroops];
1154 if ((_dest == _index) || (_dest2 == _index)) {
1155 IntRegIndex wbIndexReg = INTREG_UREG0;
1156 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1157 uops[0]->setDelayedCommit();
1158 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1159 _shiftAmt, _shiftType, _index);
1160 uops[1]->setDelayedCommit();
1161 uops[2] = new %(wb_decl)s;
1162 uops[2]->setLastMicroop();
1163 } else {
1164 IntRegIndex wbIndexReg = index;
1165 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1166 _shiftAmt, _shiftType, _index);
1167 uops[0]->setDelayedCommit();
1168 uops[1] = new %(wb_decl)s;
1169 uops[1]->setLastMicroop();
1170 }
1171#endif
1172 }
1173}};
1174
1175def template LoadRegConstructor {{
1176 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1177 uint32_t _dest, uint32_t _base, bool _add,
1178 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1179 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1180 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1181 _shiftAmt, (ArmShiftType)_shiftType,
1182 (IntRegIndex)_index)
1183 {
1184 %(constructor)s;
1185 if (!(condCode == COND_AL || condCode == COND_UC)) {
1186 for (int x = 0; x < _numDestRegs; x++) {
1187 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1188 }
1189 }
1190#if %(use_uops)d
1191 assert(numMicroops >= 2);
1192 uops = new StaticInstPtr[numMicroops];
1193 if (_dest == INTREG_PC) {
1194 IntRegIndex wbIndexReg = index;
1195 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1196 _shiftAmt, _shiftType, _index);
1197 uops[0]->setDelayedCommit();
1198 uops[1] = new %(wb_decl)s;
1199 uops[1]->setDelayedCommit();
1200 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1201 uops[2]->setLastMicroop();
1202 } else if(_dest == _index) {
1203 IntRegIndex wbIndexReg = INTREG_UREG0;
1204 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1205 uops[0]->setDelayedCommit();
1206 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1207 _shiftAmt, _shiftType, _index);
1208 uops[1]->setDelayedCommit();
1209 uops[2] = new %(wb_decl)s;
1210 uops[2]->setLastMicroop();
1211 } else {
1212 IntRegIndex wbIndexReg = index;
1213 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1214 _shiftAmt, _shiftType, _index);
1215 uops[0]->setDelayedCommit();
1216 uops[1] = new %(wb_decl)s;
1217 uops[1]->setLastMicroop();
1218
1219 }
1220#endif
1221 }
1222}};
1223
1224def template LoadImmConstructor {{
1225 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1226 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1227 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1228 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1229 {
1230 %(constructor)s;
1231 if (!(condCode == COND_AL || condCode == COND_UC)) {
1232 for (int x = 0; x < _numDestRegs; x++) {
1233 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1234 }
1235 }
1236#if %(use_uops)d
1237 assert(numMicroops >= 2);
1238 uops = new StaticInstPtr[numMicroops];
1239 if (_dest == INTREG_PC) {
1240 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1241 _imm);
1242 uops[0]->setDelayedCommit();
1243 uops[1] = new %(wb_decl)s;
1244 uops[1]->setDelayedCommit();
1245 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1246 uops[2]->setLastMicroop();
1247 } else {
1248 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1249 uops[0]->setDelayedCommit();
1250 uops[1] = new %(wb_decl)s;
1251 uops[1]->setLastMicroop();
1252 }
1253#endif
1254 }
1255}};
1256
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