1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
|
| 44def template PanicExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 panic("Execute function executed when it shouldn't be!\n");
49 return NoFault;
50 }
51}};
52
53def template PanicInitiateAcc {{
54 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
55 Trace::InstRecord *traceData) const
56 {
57 panic("InitiateAcc function executed when it shouldn't be!\n");
58 return NoFault;
59 }
60}};
61
62def template PanicCompleteAcc {{
63 Fault %(class_name)s::completeAcc(PacketPtr pkt,
64 %(CPU_exec_context)s *xc,
65 Trace::InstRecord *traceData) const
66 {
67 panic("CompleteAcc function executed when it shouldn't be!\n");
68 return NoFault;
69 }
70}};
71
72
|
44def template SwapExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;
52 uint64_t memData = 0;
53 %(op_rd)s;
54 %(ea_code)s;
55
56 if (%(predicate_test)s)
57 {
58 %(preacc_code)s;
59
60 if (fault == NoFault) {
61 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
62 EA, memAccessFlags, &memData);
63 }
64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 } else {
73 xc->setPredicate(false);
74 }
75
| 73def template SwapExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
76 {
77 Addr EA;
78 Fault fault = NoFault;
79
80 %(op_decl)s;
81 uint64_t memData = 0;
82 %(op_rd)s;
83 %(ea_code)s;
84
85 if (%(predicate_test)s)
86 {
87 %(preacc_code)s;
88
89 if (fault == NoFault) {
90 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
91 EA, memAccessFlags, &memData);
92 }
93
94 if (fault == NoFault) {
95 %(postacc_code)s;
96 }
97
98 if (fault == NoFault) {
99 %(op_wb)s;
100 }
101 } else {
102 xc->setPredicate(false);
103 }
104
|
76 if (fault == NoFault && machInst.itstateMask != 0) {
| 105 if (fault == NoFault && machInst.itstateMask != 0 &&
106 (!isMicroop() || isLastMicroop())) {
|
77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
78 }
79
80 return fault;
81 }
82}};
83
84def template SwapInitiateAcc {{
85 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
86 Trace::InstRecord *traceData) const
87 {
88 Addr EA;
89 Fault fault = NoFault;
90
91 %(op_decl)s;
92 uint64_t memData = 0;
93 %(op_rd)s;
94 %(ea_code)s;
95
96 if (%(predicate_test)s)
97 {
98 %(preacc_code)s;
99
100 if (fault == NoFault) {
101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
102 memAccessFlags, &memData);
103 }
104
105 if (fault == NoFault) {
106 %(op_wb)s;
107 }
108 } else {
109 xc->setPredicate(false);
110 }
111
| 107 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
108 }
109
110 return fault;
111 }
112}};
113
114def template SwapInitiateAcc {{
115 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
116 Trace::InstRecord *traceData) const
117 {
118 Addr EA;
119 Fault fault = NoFault;
120
121 %(op_decl)s;
122 uint64_t memData = 0;
123 %(op_rd)s;
124 %(ea_code)s;
125
126 if (%(predicate_test)s)
127 {
128 %(preacc_code)s;
129
130 if (fault == NoFault) {
131 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
132 memAccessFlags, &memData);
133 }
134
135 if (fault == NoFault) {
136 %(op_wb)s;
137 }
138 } else {
139 xc->setPredicate(false);
140 }
141
|
112 if (fault == NoFault && machInst.itstateMask != 0) {
| 142 if (fault == NoFault && machInst.itstateMask != 0 &&
143 (!isMicroop() || isLastMicroop())) {
|
113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
114 }
115
116 return fault;
117 }
118}};
119
120def template SwapCompleteAcc {{
121 Fault %(class_name)s::completeAcc(PacketPtr pkt,
122 %(CPU_exec_context)s *xc,
123 Trace::InstRecord *traceData) const
124 {
125 Fault fault = NoFault;
126
127 %(op_decl)s;
128 %(op_rd)s;
129
130 if (%(predicate_test)s)
131 {
132 // ARM instructions will not have a pkt if the predicate is false
133 uint64_t memData = pkt->get<typeof(Mem)>();
134
135 %(postacc_code)s;
136
137 if (fault == NoFault) {
138 %(op_wb)s;
139 }
140 }
141
142 if (fault == NoFault && machInst.itstateMask != 0) {
143 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
144 }
145
146 return fault;
147 }
148}};
149
150def template LoadExecute {{
151 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
152 Trace::InstRecord *traceData) const
153 {
154 Addr EA;
155 Fault fault = NoFault;
156
157 %(op_decl)s;
158 %(op_rd)s;
159 %(ea_code)s;
160
161 if (%(predicate_test)s)
162 {
163 if (fault == NoFault) {
164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
165 %(memacc_code)s;
166 }
167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 } else {
172 xc->setPredicate(false);
173 }
174
| 144 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
145 }
146
147 return fault;
148 }
149}};
150
151def template SwapCompleteAcc {{
152 Fault %(class_name)s::completeAcc(PacketPtr pkt,
153 %(CPU_exec_context)s *xc,
154 Trace::InstRecord *traceData) const
155 {
156 Fault fault = NoFault;
157
158 %(op_decl)s;
159 %(op_rd)s;
160
161 if (%(predicate_test)s)
162 {
163 // ARM instructions will not have a pkt if the predicate is false
164 uint64_t memData = pkt->get<typeof(Mem)>();
165
166 %(postacc_code)s;
167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 }
172
173 if (fault == NoFault && machInst.itstateMask != 0) {
174 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
175 }
176
177 return fault;
178 }
179}};
180
181def template LoadExecute {{
182 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
183 Trace::InstRecord *traceData) const
184 {
185 Addr EA;
186 Fault fault = NoFault;
187
188 %(op_decl)s;
189 %(op_rd)s;
190 %(ea_code)s;
191
192 if (%(predicate_test)s)
193 {
194 if (fault == NoFault) {
195 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
196 %(memacc_code)s;
197 }
198
199 if (fault == NoFault) {
200 %(op_wb)s;
201 }
202 } else {
203 xc->setPredicate(false);
204 }
205
|
175 if (fault == NoFault && machInst.itstateMask != 0) {
| 206 if (fault == NoFault && machInst.itstateMask != 0 &&
207 (!isMicroop() || isLastMicroop())) {
|
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }
181}};
182
183def template NeonLoadExecute {{
184 template <class Element>
185 Fault %(class_name)s<Element>::execute(
186 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
187 {
188 Addr EA;
189 Fault fault = NoFault;
190
191 %(op_decl)s;
192 %(mem_decl)s;
193 %(op_rd)s;
194 %(ea_code)s;
195
196 MemUnion memUnion;
197 uint8_t *dataPtr = memUnion.bytes;
198
199 if (%(predicate_test)s)
200 {
201 if (fault == NoFault) {
202 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
203 %(memacc_code)s;
204 }
205
206 if (fault == NoFault) {
207 %(op_wb)s;
208 }
209 }
210
| 208 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
209 }
210
211 return fault;
212 }
213}};
214
215def template NeonLoadExecute {{
216 template <class Element>
217 Fault %(class_name)s<Element>::execute(
218 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
219 {
220 Addr EA;
221 Fault fault = NoFault;
222
223 %(op_decl)s;
224 %(mem_decl)s;
225 %(op_rd)s;
226 %(ea_code)s;
227
228 MemUnion memUnion;
229 uint8_t *dataPtr = memUnion.bytes;
230
231 if (%(predicate_test)s)
232 {
233 if (fault == NoFault) {
234 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
235 %(memacc_code)s;
236 }
237
238 if (fault == NoFault) {
239 %(op_wb)s;
240 }
241 }
242
|
211 if (fault == NoFault && machInst.itstateMask != 0) {
| 243 if (fault == NoFault && machInst.itstateMask != 0 &&
244 (!isMicroop() || isLastMicroop())) {
|
212 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
213 }
214
215 return fault;
216 }
217}};
218
219def template StoreExecute {{
220 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
221 Trace::InstRecord *traceData) const
222 {
223 Addr EA;
224 Fault fault = NoFault;
225
226 %(op_decl)s;
227 %(op_rd)s;
228 %(ea_code)s;
229
230 if (%(predicate_test)s)
231 {
232 if (fault == NoFault) {
233 %(memacc_code)s;
234 }
235
236 if (fault == NoFault) {
237 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
238 memAccessFlags, NULL);
239 }
240
241 if (fault == NoFault) {
242 %(op_wb)s;
243 }
244 } else {
245 xc->setPredicate(false);
246 }
247
| 245 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
246 }
247
248 return fault;
249 }
250}};
251
252def template StoreExecute {{
253 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
254 Trace::InstRecord *traceData) const
255 {
256 Addr EA;
257 Fault fault = NoFault;
258
259 %(op_decl)s;
260 %(op_rd)s;
261 %(ea_code)s;
262
263 if (%(predicate_test)s)
264 {
265 if (fault == NoFault) {
266 %(memacc_code)s;
267 }
268
269 if (fault == NoFault) {
270 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
271 memAccessFlags, NULL);
272 }
273
274 if (fault == NoFault) {
275 %(op_wb)s;
276 }
277 } else {
278 xc->setPredicate(false);
279 }
280
|
248 if (fault == NoFault && machInst.itstateMask != 0) {
| 281 if (fault == NoFault && machInst.itstateMask != 0 &&
282 (!isMicroop() || isLastMicroop())) {
|
249 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
250 }
251
252 return fault;
253 }
254}};
255
256def template NeonStoreExecute {{
257 template <class Element>
258 Fault %(class_name)s<Element>::execute(
259 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
260 {
261 Addr EA;
262 Fault fault = NoFault;
263
264 %(op_decl)s;
265 %(mem_decl)s;
266 %(op_rd)s;
267 %(ea_code)s;
268
269 MemUnion memUnion;
270 uint8_t *dataPtr = memUnion.bytes;
271
272 if (%(predicate_test)s)
273 {
274 if (fault == NoFault) {
275 %(memacc_code)s;
276 }
277
278 if (fault == NoFault) {
279 fault = xc->writeBytes(dataPtr, %(size)d, EA,
280 memAccessFlags, NULL);
281 }
282
283 if (fault == NoFault) {
284 %(op_wb)s;
285 }
286 }
287
| 283 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
284 }
285
286 return fault;
287 }
288}};
289
290def template NeonStoreExecute {{
291 template <class Element>
292 Fault %(class_name)s<Element>::execute(
293 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
294 {
295 Addr EA;
296 Fault fault = NoFault;
297
298 %(op_decl)s;
299 %(mem_decl)s;
300 %(op_rd)s;
301 %(ea_code)s;
302
303 MemUnion memUnion;
304 uint8_t *dataPtr = memUnion.bytes;
305
306 if (%(predicate_test)s)
307 {
308 if (fault == NoFault) {
309 %(memacc_code)s;
310 }
311
312 if (fault == NoFault) {
313 fault = xc->writeBytes(dataPtr, %(size)d, EA,
314 memAccessFlags, NULL);
315 }
316
317 if (fault == NoFault) {
318 %(op_wb)s;
319 }
320 }
321
|
288 if (fault == NoFault && machInst.itstateMask != 0) {
| 322 if (fault == NoFault && machInst.itstateMask != 0 &&
323 (!isMicroop() || isLastMicroop())) {
|
289 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
290 }
291
292 return fault;
293 }
294}};
295
296def template StoreExExecute {{
297 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
298 Trace::InstRecord *traceData) const
299 {
300 Addr EA;
301 Fault fault = NoFault;
302
303 %(op_decl)s;
304 %(op_rd)s;
305 %(ea_code)s;
306
307 if (%(predicate_test)s)
308 {
309 if (fault == NoFault) {
310 %(memacc_code)s;
311 }
312
313 uint64_t writeResult;
314
315 if (fault == NoFault) {
316 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
317 memAccessFlags, &writeResult);
318 }
319
320 if (fault == NoFault) {
321 %(postacc_code)s;
322 }
323
324 if (fault == NoFault) {
325 %(op_wb)s;
326 }
327 } else {
328 xc->setPredicate(false);
329 }
330
| 324 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
325 }
326
327 return fault;
328 }
329}};
330
331def template StoreExExecute {{
332 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
333 Trace::InstRecord *traceData) const
334 {
335 Addr EA;
336 Fault fault = NoFault;
337
338 %(op_decl)s;
339 %(op_rd)s;
340 %(ea_code)s;
341
342 if (%(predicate_test)s)
343 {
344 if (fault == NoFault) {
345 %(memacc_code)s;
346 }
347
348 uint64_t writeResult;
349
350 if (fault == NoFault) {
351 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
352 memAccessFlags, &writeResult);
353 }
354
355 if (fault == NoFault) {
356 %(postacc_code)s;
357 }
358
359 if (fault == NoFault) {
360 %(op_wb)s;
361 }
362 } else {
363 xc->setPredicate(false);
364 }
365
|
331 if (fault == NoFault && machInst.itstateMask != 0) {
| 366 if (fault == NoFault && machInst.itstateMask != 0 &&
367 (!isMicroop() || isLastMicroop())) {
|
332 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
333 }
334
335 return fault;
336 }
337}};
338
339def template StoreExInitiateAcc {{
340 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
341 Trace::InstRecord *traceData) const
342 {
343 Addr EA;
344 Fault fault = NoFault;
345
346 %(op_decl)s;
347 %(op_rd)s;
348 %(ea_code)s;
349
350 if (%(predicate_test)s)
351 {
352 if (fault == NoFault) {
353 %(memacc_code)s;
354 }
355
356 if (fault == NoFault) {
357 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
358 memAccessFlags, NULL);
359 }
360
361 // Need to write back any potential address register update
362 if (fault == NoFault) {
363 %(op_wb)s;
364 }
365 } else {
366 xc->setPredicate(false);
367 }
| 368 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
369 }
370
371 return fault;
372 }
373}};
374
375def template StoreExInitiateAcc {{
376 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
377 Trace::InstRecord *traceData) const
378 {
379 Addr EA;
380 Fault fault = NoFault;
381
382 %(op_decl)s;
383 %(op_rd)s;
384 %(ea_code)s;
385
386 if (%(predicate_test)s)
387 {
388 if (fault == NoFault) {
389 %(memacc_code)s;
390 }
391
392 if (fault == NoFault) {
393 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
394 memAccessFlags, NULL);
395 }
396
397 // Need to write back any potential address register update
398 if (fault == NoFault) {
399 %(op_wb)s;
400 }
401 } else {
402 xc->setPredicate(false);
403 }
|
368
369 if (fault == NoFault && machInst.itstateMask != 0) {
| 404 if (fault == NoFault && machInst.itstateMask != 0 &&
405 (!isMicroop() || isLastMicroop())) {
|
370 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
371 }
372
373 return fault;
374 }
375}};
376
377def template StoreInitiateAcc {{
378 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
379 Trace::InstRecord *traceData) const
380 {
381 Addr EA;
382 Fault fault = NoFault;
383
384 %(op_decl)s;
385 %(op_rd)s;
386 %(ea_code)s;
387
388 if (%(predicate_test)s)
389 {
390 if (fault == NoFault) {
391 %(memacc_code)s;
392 }
393
394 if (fault == NoFault) {
395 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
396 memAccessFlags, NULL);
397 }
398
399 // Need to write back any potential address register update
400 if (fault == NoFault) {
401 %(op_wb)s;
402 }
403 } else {
404 xc->setPredicate(false);
405 }
406
| 406 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
407 }
408
409 return fault;
410 }
411}};
412
413def template StoreInitiateAcc {{
414 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
415 Trace::InstRecord *traceData) const
416 {
417 Addr EA;
418 Fault fault = NoFault;
419
420 %(op_decl)s;
421 %(op_rd)s;
422 %(ea_code)s;
423
424 if (%(predicate_test)s)
425 {
426 if (fault == NoFault) {
427 %(memacc_code)s;
428 }
429
430 if (fault == NoFault) {
431 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
432 memAccessFlags, NULL);
433 }
434
435 // Need to write back any potential address register update
436 if (fault == NoFault) {
437 %(op_wb)s;
438 }
439 } else {
440 xc->setPredicate(false);
441 }
442
|
407 if (fault == NoFault && machInst.itstateMask != 0) {
| 443 if (fault == NoFault && machInst.itstateMask != 0 &&
444 (!isMicroop() || isLastMicroop())) {
|
408 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
409 }
410
411 return fault;
412 }
413}};
414
415def template NeonStoreInitiateAcc {{
416 template <class Element>
417 Fault %(class_name)s<Element>::initiateAcc(
418 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
419 {
420 Addr EA;
421 Fault fault = NoFault;
422
423 %(op_decl)s;
424 %(mem_decl)s;
425 %(op_rd)s;
426 %(ea_code)s;
427
428 if (%(predicate_test)s)
429 {
430 MemUnion memUnion;
431 if (fault == NoFault) {
432 %(memacc_code)s;
433 }
434
435 if (fault == NoFault) {
436 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
437 memAccessFlags, NULL);
438 }
439
440 // Need to write back any potential address register update
441 if (fault == NoFault) {
442 %(op_wb)s;
443 }
444 }
445
| 445 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
446 }
447
448 return fault;
449 }
450}};
451
452def template NeonStoreInitiateAcc {{
453 template <class Element>
454 Fault %(class_name)s<Element>::initiateAcc(
455 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
456 {
457 Addr EA;
458 Fault fault = NoFault;
459
460 %(op_decl)s;
461 %(mem_decl)s;
462 %(op_rd)s;
463 %(ea_code)s;
464
465 if (%(predicate_test)s)
466 {
467 MemUnion memUnion;
468 if (fault == NoFault) {
469 %(memacc_code)s;
470 }
471
472 if (fault == NoFault) {
473 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
474 memAccessFlags, NULL);
475 }
476
477 // Need to write back any potential address register update
478 if (fault == NoFault) {
479 %(op_wb)s;
480 }
481 }
482
|
446 if (fault == NoFault && machInst.itstateMask != 0) {
| 483 if (fault == NoFault && machInst.itstateMask != 0 &&
484 (!isMicroop() || isLastMicroop())) {
|
447 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
448 }
449
450 return fault;
451 }
452}};
453
454def template LoadInitiateAcc {{
455 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
456 Trace::InstRecord *traceData) const
457 {
458 Addr EA;
459 Fault fault = NoFault;
460
461 %(op_src_decl)s;
462 %(op_rd)s;
463 %(ea_code)s;
464
465 if (%(predicate_test)s)
466 {
467 if (fault == NoFault) {
468 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
469 }
470 } else {
471 xc->setPredicate(false);
| 485 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
486 }
487
488 return fault;
489 }
490}};
491
492def template LoadInitiateAcc {{
493 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
494 Trace::InstRecord *traceData) const
495 {
496 Addr EA;
497 Fault fault = NoFault;
498
499 %(op_src_decl)s;
500 %(op_rd)s;
501 %(ea_code)s;
502
503 if (%(predicate_test)s)
504 {
505 if (fault == NoFault) {
506 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
507 }
508 } else {
509 xc->setPredicate(false);
|
472 if (fault == NoFault && machInst.itstateMask != 0) {
| 510 if (fault == NoFault && machInst.itstateMask != 0 &&
511 (!isMicroop() || isLastMicroop())) {
|
473 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
474 }
475 }
476
477 return fault;
478 }
479}};
480
481def template NeonLoadInitiateAcc {{
482 template <class Element>
483 Fault %(class_name)s<Element>::initiateAcc(
484 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
485 {
486 Addr EA;
487 Fault fault = NoFault;
488
489 %(op_src_decl)s;
490 %(op_rd)s;
491 %(ea_code)s;
492
493 if (%(predicate_test)s)
494 {
495 if (fault == NoFault) {
496 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
497 }
| 512 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
513 }
514 }
515
516 return fault;
517 }
518}};
519
520def template NeonLoadInitiateAcc {{
521 template <class Element>
522 Fault %(class_name)s<Element>::initiateAcc(
523 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
524 {
525 Addr EA;
526 Fault fault = NoFault;
527
528 %(op_src_decl)s;
529 %(op_rd)s;
530 %(ea_code)s;
531
532 if (%(predicate_test)s)
533 {
534 if (fault == NoFault) {
535 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
536 }
|
498 } else if (fault == NoFault && machInst.itstateMask != 0) {
| 537 } else if (fault == NoFault && machInst.itstateMask != 0 &&
538 (!isMicroop() || isLastMicroop())) {
|
499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
500 }
501
502 return fault;
503 }
504}};
505
506def template LoadCompleteAcc {{
507 Fault %(class_name)s::completeAcc(PacketPtr pkt,
508 %(CPU_exec_context)s *xc,
509 Trace::InstRecord *traceData) const
510 {
511 Fault fault = NoFault;
512
513 %(op_decl)s;
514 %(op_rd)s;
515
516 if (%(predicate_test)s)
517 {
518 // ARM instructions will not have a pkt if the predicate is false
519 Mem = pkt->get<typeof(Mem)>();
520
521 if (fault == NoFault) {
522 %(memacc_code)s;
523 }
524
525 if (fault == NoFault) {
526 %(op_wb)s;
527 }
528 }
529
530 if (fault == NoFault && machInst.itstateMask != 0) {
531 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
532 }
533
534 return fault;
535 }
536}};
537
538def template NeonLoadCompleteAcc {{
539 template <class Element>
540 Fault %(class_name)s<Element>::completeAcc(
541 PacketPtr pkt, %(CPU_exec_context)s *xc,
542 Trace::InstRecord *traceData) const
543 {
544 Fault fault = NoFault;
545
546 %(mem_decl)s;
547 %(op_decl)s;
548 %(op_rd)s;
549
550 if (%(predicate_test)s)
551 {
552 // ARM instructions will not have a pkt if the predicate is false
553 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
554
555 if (fault == NoFault) {
556 %(memacc_code)s;
557 }
558
559 if (fault == NoFault) {
560 %(op_wb)s;
561 }
562 }
563
564 if (fault == NoFault && machInst.itstateMask != 0) {
565 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
566 }
567
568 return fault;
569 }
570}};
571
572def template StoreCompleteAcc {{
573 Fault %(class_name)s::completeAcc(PacketPtr pkt,
574 %(CPU_exec_context)s *xc,
575 Trace::InstRecord *traceData) const
576 {
577 Fault fault = NoFault;
578
579 %(op_decl)s;
580 %(op_rd)s;
581
582 if (%(predicate_test)s)
583 {
584 if (fault == NoFault) {
585 %(op_wb)s;
586 }
587 }
588
589 if (fault == NoFault && machInst.itstateMask != 0) {
590 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
591 }
592
593 return fault;
594 }
595}};
596
597def template NeonStoreCompleteAcc {{
598 template <class Element>
599 Fault %(class_name)s<Element>::completeAcc(
600 PacketPtr pkt, %(CPU_exec_context)s *xc,
601 Trace::InstRecord *traceData) const
602 {
603 Fault fault = NoFault;
604
605 %(op_decl)s;
606 %(op_rd)s;
607
608 if (%(predicate_test)s)
609 {
610 if (fault == NoFault) {
611 %(op_wb)s;
612 }
613 }
614
615 if (fault == NoFault && machInst.itstateMask != 0) {
616 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
617 }
618
619 return fault;
620 }
621}};
622
623def template StoreExCompleteAcc {{
624 Fault %(class_name)s::completeAcc(PacketPtr pkt,
625 %(CPU_exec_context)s *xc,
626 Trace::InstRecord *traceData) const
627 {
628 Fault fault = NoFault;
629
630 %(op_decl)s;
631 %(op_rd)s;
632
633 if (%(predicate_test)s)
634 {
635 uint64_t writeResult = pkt->req->getExtraData();
636 %(postacc_code)s;
637
638 if (fault == NoFault) {
639 %(op_wb)s;
640 }
641 }
642
643 if (fault == NoFault && machInst.itstateMask != 0) {
644 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
645 }
646
647 return fault;
648 }
649}};
650
651def template RfeDeclare {{
652 /**
653 * Static instruction class for "%(mnemonic)s".
654 */
655 class %(class_name)s : public %(base_class)s
656 {
657 public:
658
659 /// Constructor.
660 %(class_name)s(ExtMachInst machInst,
661 uint32_t _base, int _mode, bool _wb);
662
663 %(BasicExecDeclare)s
664
665 %(InitiateAccDeclare)s
666
667 %(CompleteAccDeclare)s
668 };
669}};
670
671def template SrsDeclare {{
672 /**
673 * Static instruction class for "%(mnemonic)s".
674 */
675 class %(class_name)s : public %(base_class)s
676 {
677 public:
678
679 /// Constructor.
680 %(class_name)s(ExtMachInst machInst,
681 uint32_t _regMode, int _mode, bool _wb);
682
683 %(BasicExecDeclare)s
684
685 %(InitiateAccDeclare)s
686
687 %(CompleteAccDeclare)s
688 };
689}};
690
691def template SwapDeclare {{
692 /**
693 * Static instruction class for "%(mnemonic)s".
694 */
695 class %(class_name)s : public %(base_class)s
696 {
697 public:
698
699 /// Constructor.
700 %(class_name)s(ExtMachInst machInst,
701 uint32_t _dest, uint32_t _op1, uint32_t _base);
702
703 %(BasicExecDeclare)s
704
705 %(InitiateAccDeclare)s
706
707 %(CompleteAccDeclare)s
708 };
709}};
710
711def template LoadStoreDImmDeclare {{
712 /**
713 * Static instruction class for "%(mnemonic)s".
714 */
715 class %(class_name)s : public %(base_class)s
716 {
717 public:
718
719 /// Constructor.
720 %(class_name)s(ExtMachInst machInst,
721 uint32_t _dest, uint32_t _dest2,
722 uint32_t _base, bool _add, int32_t _imm);
723
724 %(BasicExecDeclare)s
725
726 %(InitiateAccDeclare)s
727
728 %(CompleteAccDeclare)s
729 };
730}};
731
732def template StoreExDImmDeclare {{
733 /**
734 * Static instruction class for "%(mnemonic)s".
735 */
736 class %(class_name)s : public %(base_class)s
737 {
738 public:
739
740 /// Constructor.
741 %(class_name)s(ExtMachInst machInst,
742 uint32_t _result, uint32_t _dest, uint32_t _dest2,
743 uint32_t _base, bool _add, int32_t _imm);
744
745 %(BasicExecDeclare)s
746
747 %(InitiateAccDeclare)s
748
749 %(CompleteAccDeclare)s
750 };
751}};
752
753def template LoadStoreImmDeclare {{
754 /**
755 * Static instruction class for "%(mnemonic)s".
756 */
757 class %(class_name)s : public %(base_class)s
758 {
759 public:
760
761 /// Constructor.
762 %(class_name)s(ExtMachInst machInst,
763 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
764
765 %(BasicExecDeclare)s
766
767 %(InitiateAccDeclare)s
768
769 %(CompleteAccDeclare)s
770 };
771}};
772
773def template StoreExImmDeclare {{
774 /**
775 * Static instruction class for "%(mnemonic)s".
776 */
777 class %(class_name)s : public %(base_class)s
778 {
779 public:
780
781 /// Constructor.
782 %(class_name)s(ExtMachInst machInst,
783 uint32_t _result, uint32_t _dest, uint32_t _base,
784 bool _add, int32_t _imm);
785
786 %(BasicExecDeclare)s
787
788 %(InitiateAccDeclare)s
789
790 %(CompleteAccDeclare)s
791 };
792}};
793
| 539 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
540 }
541
542 return fault;
543 }
544}};
545
546def template LoadCompleteAcc {{
547 Fault %(class_name)s::completeAcc(PacketPtr pkt,
548 %(CPU_exec_context)s *xc,
549 Trace::InstRecord *traceData) const
550 {
551 Fault fault = NoFault;
552
553 %(op_decl)s;
554 %(op_rd)s;
555
556 if (%(predicate_test)s)
557 {
558 // ARM instructions will not have a pkt if the predicate is false
559 Mem = pkt->get<typeof(Mem)>();
560
561 if (fault == NoFault) {
562 %(memacc_code)s;
563 }
564
565 if (fault == NoFault) {
566 %(op_wb)s;
567 }
568 }
569
570 if (fault == NoFault && machInst.itstateMask != 0) {
571 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
572 }
573
574 return fault;
575 }
576}};
577
578def template NeonLoadCompleteAcc {{
579 template <class Element>
580 Fault %(class_name)s<Element>::completeAcc(
581 PacketPtr pkt, %(CPU_exec_context)s *xc,
582 Trace::InstRecord *traceData) const
583 {
584 Fault fault = NoFault;
585
586 %(mem_decl)s;
587 %(op_decl)s;
588 %(op_rd)s;
589
590 if (%(predicate_test)s)
591 {
592 // ARM instructions will not have a pkt if the predicate is false
593 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
594
595 if (fault == NoFault) {
596 %(memacc_code)s;
597 }
598
599 if (fault == NoFault) {
600 %(op_wb)s;
601 }
602 }
603
604 if (fault == NoFault && machInst.itstateMask != 0) {
605 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
606 }
607
608 return fault;
609 }
610}};
611
612def template StoreCompleteAcc {{
613 Fault %(class_name)s::completeAcc(PacketPtr pkt,
614 %(CPU_exec_context)s *xc,
615 Trace::InstRecord *traceData) const
616 {
617 Fault fault = NoFault;
618
619 %(op_decl)s;
620 %(op_rd)s;
621
622 if (%(predicate_test)s)
623 {
624 if (fault == NoFault) {
625 %(op_wb)s;
626 }
627 }
628
629 if (fault == NoFault && machInst.itstateMask != 0) {
630 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
631 }
632
633 return fault;
634 }
635}};
636
637def template NeonStoreCompleteAcc {{
638 template <class Element>
639 Fault %(class_name)s<Element>::completeAcc(
640 PacketPtr pkt, %(CPU_exec_context)s *xc,
641 Trace::InstRecord *traceData) const
642 {
643 Fault fault = NoFault;
644
645 %(op_decl)s;
646 %(op_rd)s;
647
648 if (%(predicate_test)s)
649 {
650 if (fault == NoFault) {
651 %(op_wb)s;
652 }
653 }
654
655 if (fault == NoFault && machInst.itstateMask != 0) {
656 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
657 }
658
659 return fault;
660 }
661}};
662
663def template StoreExCompleteAcc {{
664 Fault %(class_name)s::completeAcc(PacketPtr pkt,
665 %(CPU_exec_context)s *xc,
666 Trace::InstRecord *traceData) const
667 {
668 Fault fault = NoFault;
669
670 %(op_decl)s;
671 %(op_rd)s;
672
673 if (%(predicate_test)s)
674 {
675 uint64_t writeResult = pkt->req->getExtraData();
676 %(postacc_code)s;
677
678 if (fault == NoFault) {
679 %(op_wb)s;
680 }
681 }
682
683 if (fault == NoFault && machInst.itstateMask != 0) {
684 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
685 }
686
687 return fault;
688 }
689}};
690
691def template RfeDeclare {{
692 /**
693 * Static instruction class for "%(mnemonic)s".
694 */
695 class %(class_name)s : public %(base_class)s
696 {
697 public:
698
699 /// Constructor.
700 %(class_name)s(ExtMachInst machInst,
701 uint32_t _base, int _mode, bool _wb);
702
703 %(BasicExecDeclare)s
704
705 %(InitiateAccDeclare)s
706
707 %(CompleteAccDeclare)s
708 };
709}};
710
711def template SrsDeclare {{
712 /**
713 * Static instruction class for "%(mnemonic)s".
714 */
715 class %(class_name)s : public %(base_class)s
716 {
717 public:
718
719 /// Constructor.
720 %(class_name)s(ExtMachInst machInst,
721 uint32_t _regMode, int _mode, bool _wb);
722
723 %(BasicExecDeclare)s
724
725 %(InitiateAccDeclare)s
726
727 %(CompleteAccDeclare)s
728 };
729}};
730
731def template SwapDeclare {{
732 /**
733 * Static instruction class for "%(mnemonic)s".
734 */
735 class %(class_name)s : public %(base_class)s
736 {
737 public:
738
739 /// Constructor.
740 %(class_name)s(ExtMachInst machInst,
741 uint32_t _dest, uint32_t _op1, uint32_t _base);
742
743 %(BasicExecDeclare)s
744
745 %(InitiateAccDeclare)s
746
747 %(CompleteAccDeclare)s
748 };
749}};
750
751def template LoadStoreDImmDeclare {{
752 /**
753 * Static instruction class for "%(mnemonic)s".
754 */
755 class %(class_name)s : public %(base_class)s
756 {
757 public:
758
759 /// Constructor.
760 %(class_name)s(ExtMachInst machInst,
761 uint32_t _dest, uint32_t _dest2,
762 uint32_t _base, bool _add, int32_t _imm);
763
764 %(BasicExecDeclare)s
765
766 %(InitiateAccDeclare)s
767
768 %(CompleteAccDeclare)s
769 };
770}};
771
772def template StoreExDImmDeclare {{
773 /**
774 * Static instruction class for "%(mnemonic)s".
775 */
776 class %(class_name)s : public %(base_class)s
777 {
778 public:
779
780 /// Constructor.
781 %(class_name)s(ExtMachInst machInst,
782 uint32_t _result, uint32_t _dest, uint32_t _dest2,
783 uint32_t _base, bool _add, int32_t _imm);
784
785 %(BasicExecDeclare)s
786
787 %(InitiateAccDeclare)s
788
789 %(CompleteAccDeclare)s
790 };
791}};
792
793def template LoadStoreImmDeclare {{
794 /**
795 * Static instruction class for "%(mnemonic)s".
796 */
797 class %(class_name)s : public %(base_class)s
798 {
799 public:
800
801 /// Constructor.
802 %(class_name)s(ExtMachInst machInst,
803 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
804
805 %(BasicExecDeclare)s
806
807 %(InitiateAccDeclare)s
808
809 %(CompleteAccDeclare)s
810 };
811}};
812
813def template StoreExImmDeclare {{
814 /**
815 * Static instruction class for "%(mnemonic)s".
816 */
817 class %(class_name)s : public %(base_class)s
818 {
819 public:
820
821 /// Constructor.
822 %(class_name)s(ExtMachInst machInst,
823 uint32_t _result, uint32_t _dest, uint32_t _base,
824 bool _add, int32_t _imm);
825
826 %(BasicExecDeclare)s
827
828 %(InitiateAccDeclare)s
829
830 %(CompleteAccDeclare)s
831 };
832}};
833
|
794def template LoadStoreDRegDeclare {{
| 834def template StoreDRegDeclare {{
|
795 /**
796 * Static instruction class for "%(mnemonic)s".
797 */
798 class %(class_name)s : public %(base_class)s
799 {
800 public:
801
802 /// Constructor.
803 %(class_name)s(ExtMachInst machInst,
804 uint32_t _dest, uint32_t _dest2,
805 uint32_t _base, bool _add,
806 int32_t _shiftAmt, uint32_t _shiftType,
807 uint32_t _index);
808
809 %(BasicExecDeclare)s
810
811 %(InitiateAccDeclare)s
812
813 %(CompleteAccDeclare)s
814 };
815}};
816
| 835 /**
836 * Static instruction class for "%(mnemonic)s".
837 */
838 class %(class_name)s : public %(base_class)s
839 {
840 public:
841
842 /// Constructor.
843 %(class_name)s(ExtMachInst machInst,
844 uint32_t _dest, uint32_t _dest2,
845 uint32_t _base, bool _add,
846 int32_t _shiftAmt, uint32_t _shiftType,
847 uint32_t _index);
848
849 %(BasicExecDeclare)s
850
851 %(InitiateAccDeclare)s
852
853 %(CompleteAccDeclare)s
854 };
855}};
856
|
817def template LoadStoreRegDeclare {{
| 857def template StoreRegDeclare {{
|
818 /**
819 * Static instruction class for "%(mnemonic)s".
820 */
821 class %(class_name)s : public %(base_class)s
822 {
823 public:
824
825 /// Constructor.
826 %(class_name)s(ExtMachInst machInst,
827 uint32_t _dest, uint32_t _base, bool _add,
828 int32_t _shiftAmt, uint32_t _shiftType,
829 uint32_t _index);
830
831 %(BasicExecDeclare)s
832
833 %(InitiateAccDeclare)s
834
835 %(CompleteAccDeclare)s
836 };
837}};
838
| 858 /**
859 * Static instruction class for "%(mnemonic)s".
860 */
861 class %(class_name)s : public %(base_class)s
862 {
863 public:
864
865 /// Constructor.
866 %(class_name)s(ExtMachInst machInst,
867 uint32_t _dest, uint32_t _base, bool _add,
868 int32_t _shiftAmt, uint32_t _shiftType,
869 uint32_t _index);
870
871 %(BasicExecDeclare)s
872
873 %(InitiateAccDeclare)s
874
875 %(CompleteAccDeclare)s
876 };
877}};
878
|
| 879def template LoadDRegDeclare {{
880 /**
881 * Static instruction class for "%(mnemonic)s".
882 */
883 class %(class_name)s : public %(base_class)s
884 {
885 public:
886
887 /// Constructor.
888 %(class_name)s(ExtMachInst machInst,
889 uint32_t _dest, uint32_t _dest2,
890 uint32_t _base, bool _add,
891 int32_t _shiftAmt, uint32_t _shiftType,
892 uint32_t _index);
893
894 %(BasicExecDeclare)s
895
896 %(InitiateAccDeclare)s
897
898 %(CompleteAccDeclare)s
899 };
900}};
901
902def template LoadRegDeclare {{
903 /**
904 * Static instruction class for "%(mnemonic)s".
905 */
906 class %(class_name)s : public %(base_class)s
907 {
908 public:
909
910 /// Constructor.
911 %(class_name)s(ExtMachInst machInst,
912 uint32_t _dest, uint32_t _base, bool _add,
913 int32_t _shiftAmt, uint32_t _shiftType,
914 uint32_t _index);
915
916 %(BasicExecDeclare)s
917
918 %(InitiateAccDeclare)s
919
920 %(CompleteAccDeclare)s
921 };
922}};
923
924def template LoadImmDeclare {{
925 /**
926 * Static instruction class for "%(mnemonic)s".
927 */
928 class %(class_name)s : public %(base_class)s
929 {
930 public:
931
932 /// Constructor.
933 %(class_name)s(ExtMachInst machInst,
934 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
935
936 %(BasicExecDeclare)s
937
938 %(InitiateAccDeclare)s
939
940 %(CompleteAccDeclare)s
941 };
942}};
943
|
839def template InitiateAccDeclare {{
840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
841}};
842
843def template CompleteAccDeclare {{
844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
845}};
846
847def template RfeConstructor {{
848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 uint32_t _base, int _mode, bool _wb)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 (IntRegIndex)_base, (AddrMode)_mode, _wb)
852 {
853 %(constructor)s;
| 944def template InitiateAccDeclare {{
945 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
946}};
947
948def template CompleteAccDeclare {{
949 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
950}};
951
952def template RfeConstructor {{
953 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
954 uint32_t _base, int _mode, bool _wb)
955 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
956 (IntRegIndex)_base, (AddrMode)_mode, _wb)
957 {
958 %(constructor)s;
|
| 959#if %(use_uops)d
960 assert(numMicroops >= 2);
961 uops = new StaticInstPtr[numMicroops];
962 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
963 uops[1] = new %(wb_decl)s;
964 uops[1]->setLastMicroop();
965#endif
|
854 }
855}};
856
857def template SrsConstructor {{
858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
859 uint32_t _regMode, int _mode, bool _wb)
860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
861 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
862 {
863 %(constructor)s;
| 966 }
967}};
968
969def template SrsConstructor {{
970 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
971 uint32_t _regMode, int _mode, bool _wb)
972 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
973 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
974 {
975 %(constructor)s;
|
| 976#if %(use_uops)d
977 assert(numMicroops >= 2);
978 uops = new StaticInstPtr[numMicroops];
979 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
980 uops[1] = new %(wb_decl)s;
981 uops[1]->setLastMicroop();
982#endif
|
864 }
865}};
866
867def template SwapConstructor {{
868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
869 uint32_t _dest, uint32_t _op1, uint32_t _base)
870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
872 {
873 %(constructor)s;
874 }
875}};
876
877def template LoadStoreDImmConstructor {{
878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
879 uint32_t _dest, uint32_t _dest2,
880 uint32_t _base, bool _add, int32_t _imm)
881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
882 (IntRegIndex)_dest, (IntRegIndex)_dest2,
883 (IntRegIndex)_base, _add, _imm)
884 {
885 %(constructor)s;
| 983 }
984}};
985
986def template SwapConstructor {{
987 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
988 uint32_t _dest, uint32_t _op1, uint32_t _base)
989 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
990 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
991 {
992 %(constructor)s;
993 }
994}};
995
996def template LoadStoreDImmConstructor {{
997 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
998 uint32_t _dest, uint32_t _dest2,
999 uint32_t _base, bool _add, int32_t _imm)
1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1001 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1002 (IntRegIndex)_base, _add, _imm)
1003 {
1004 %(constructor)s;
|
| 1005#if %(use_uops)d
1006 assert(numMicroops >= 2);
1007 uops = new StaticInstPtr[numMicroops];
1008 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
1009 uops[1] = new %(wb_decl)s;
1010 uops[1]->setLastMicroop();
1011#endif
|
886 }
887}};
888
889def template StoreExDImmConstructor {{
890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
891 uint32_t _result, uint32_t _dest, uint32_t _dest2,
892 uint32_t _base, bool _add, int32_t _imm)
893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
894 (IntRegIndex)_result,
895 (IntRegIndex)_dest, (IntRegIndex)_dest2,
896 (IntRegIndex)_base, _add, _imm)
897 {
898 %(constructor)s;
| 1012 }
1013}};
1014
1015def template StoreExDImmConstructor {{
1016 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1017 uint32_t _result, uint32_t _dest, uint32_t _dest2,
1018 uint32_t _base, bool _add, int32_t _imm)
1019 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1020 (IntRegIndex)_result,
1021 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1022 (IntRegIndex)_base, _add, _imm)
1023 {
1024 %(constructor)s;
|
| 1025#if %(use_uops)d
1026 assert(numMicroops >= 2);
1027 uops = new StaticInstPtr[numMicroops];
1028 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
1029 _base, _add, _imm);
1030 uops[1] = new %(wb_decl)s;
1031 uops[1]->setLastMicroop();
1032#endif
|
899 }
900}};
901
902def template LoadStoreImmConstructor {{
903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
907 {
908 %(constructor)s;
| 1033 }
1034}};
1035
1036def template LoadStoreImmConstructor {{
1037 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1038 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1039 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1040 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1041 {
1042 %(constructor)s;
|
| 1043#if %(use_uops)d
1044 assert(numMicroops >= 2);
1045 uops = new StaticInstPtr[numMicroops];
1046 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1047 uops[1] = new %(wb_decl)s;
1048 uops[1]->setLastMicroop();
1049#endif
|
909 }
910}};
911
912def template StoreExImmConstructor {{
913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
914 uint32_t _result, uint32_t _dest, uint32_t _base,
915 bool _add, int32_t _imm)
916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
917 (IntRegIndex)_result, (IntRegIndex)_dest,
918 (IntRegIndex)_base, _add, _imm)
919 {
920 %(constructor)s;
| 1050 }
1051}};
1052
1053def template StoreExImmConstructor {{
1054 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1055 uint32_t _result, uint32_t _dest, uint32_t _base,
1056 bool _add, int32_t _imm)
1057 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1058 (IntRegIndex)_result, (IntRegIndex)_dest,
1059 (IntRegIndex)_base, _add, _imm)
1060 {
1061 %(constructor)s;
|
| 1062#if %(use_uops)d
1063 assert(numMicroops >= 2);
1064 uops = new StaticInstPtr[numMicroops];
1065 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1066 _base, _add, _imm);
1067 uops[1] = new %(wb_decl)s;
1068 uops[1]->setLastMicroop();
1069#endif
|
921 }
922}};
923
| 1070 }
1071}};
1072
|
924def template LoadStoreDRegConstructor {{
| 1073def template StoreDRegConstructor {{
|
925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
929 (IntRegIndex)_dest, (IntRegIndex)_dest2,
930 (IntRegIndex)_base, _add,
931 _shiftAmt, (ArmShiftType)_shiftType,
932 (IntRegIndex)_index)
933 {
934 %(constructor)s;
| 1074 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1075 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1076 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1077 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1078 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1079 (IntRegIndex)_base, _add,
1080 _shiftAmt, (ArmShiftType)_shiftType,
1081 (IntRegIndex)_index)
1082 {
1083 %(constructor)s;
|
| 1084#if %(use_uops)d
1085 assert(numMicroops >= 2);
1086 uops = new StaticInstPtr[numMicroops];
1087 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1088 _shiftAmt, _shiftType, _index);
1089 uops[1] = new %(wb_decl)s;
1090 uops[1]->setLastMicroop();
1091#endif
|
935 }
936}};
937
| 1092 }
1093}};
1094
|
938def template LoadStoreRegConstructor {{
| 1095def template StoreRegConstructor {{
|
939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
940 uint32_t _dest, uint32_t _base, bool _add,
941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
943 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
944 _shiftAmt, (ArmShiftType)_shiftType,
945 (IntRegIndex)_index)
946 {
947 %(constructor)s;
| 1096 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1097 uint32_t _dest, uint32_t _base, bool _add,
1098 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1099 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1100 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1101 _shiftAmt, (ArmShiftType)_shiftType,
1102 (IntRegIndex)_index)
1103 {
1104 %(constructor)s;
|
| 1105#if %(use_uops)d
1106 assert(numMicroops >= 2);
1107 uops = new StaticInstPtr[numMicroops];
1108 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1109 _shiftAmt, _shiftType, _index);
1110 uops[1] = new %(wb_decl)s;
1111 uops[1]->setLastMicroop();
1112#endif
|
948 }
949}};
| 1113 }
1114}};
|
| 1115
1116def template LoadDRegConstructor {{
1117 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1118 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1119 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1121 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1122 (IntRegIndex)_base, _add,
1123 _shiftAmt, (ArmShiftType)_shiftType,
1124 (IntRegIndex)_index)
1125 {
1126 %(constructor)s;
1127#if %(use_uops)d
1128 assert(numMicroops >= 2);
1129 uops = new StaticInstPtr[numMicroops];
1130 if ((_dest == _index) || (_dest2 == _index)) {
1131 IntRegIndex wbIndexReg = INTREG_UREG0;
1132 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1133 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1134 _shiftAmt, _shiftType, _index);
1135 uops[2] = new %(wb_decl)s;
1136 uops[2]->setLastMicroop();
1137 } else {
1138 IntRegIndex wbIndexReg = index;
1139 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1140 _shiftAmt, _shiftType, _index);
1141 uops[1] = new %(wb_decl)s;
1142 uops[1]->setLastMicroop();
1143 }
1144#endif
1145 }
1146}};
1147
1148def template LoadRegConstructor {{
1149 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1150 uint32_t _dest, uint32_t _base, bool _add,
1151 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1152 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1153 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1154 _shiftAmt, (ArmShiftType)_shiftType,
1155 (IntRegIndex)_index)
1156 {
1157 %(constructor)s;
1158#if %(use_uops)d
1159 assert(numMicroops >= 2);
1160 uops = new StaticInstPtr[numMicroops];
1161 if (_dest == INTREG_PC) {
1162 IntRegIndex wbIndexReg = index;
1163 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1164 _shiftAmt, _shiftType, _index);
1165 uops[1] = new %(wb_decl)s;
1166 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1167 uops[2]->setLastMicroop();
1168 } else if(_dest == _index) {
1169 IntRegIndex wbIndexReg = INTREG_UREG0;
1170 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1171 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1172 _shiftAmt, _shiftType, _index);
1173 uops[2] = new %(wb_decl)s;
1174 uops[2]->setLastMicroop();
1175 } else {
1176 IntRegIndex wbIndexReg = index;
1177 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1178 _shiftAmt, _shiftType, _index);
1179 uops[1] = new %(wb_decl)s;
1180 uops[1]->setLastMicroop();
1181
1182 }
1183#endif
1184 }
1185}};
1186
1187def template LoadImmConstructor {{
1188 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1189 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1190 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1191 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1192 {
1193 %(constructor)s;
1194#if %(use_uops)d
1195 assert(numMicroops >= 2);
1196 uops = new StaticInstPtr[numMicroops];
1197 if (_dest == INTREG_PC) {
1198 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1199 _imm);
1200 uops[1] = new %(wb_decl)s;
1201 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1202 uops[2]->setLastMicroop();
1203 } else {
1204 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1205 uops[1] = new %(wb_decl)s;
1206 uops[1]->setLastMicroop();
1207 }
1208#endif
1209 }
1210}};
1211
|
| |