1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43 44def template SwapExecute {{ 45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 46 Trace::InstRecord *traceData) const 47 { 48 Addr EA; 49 Fault fault = NoFault; 50 51 %(op_decl)s; 52 uint64_t memData = 0; 53 %(op_rd)s; 54 %(ea_code)s; 55 56 if (%(predicate_test)s) 57 { 58 %(preacc_code)s; 59 60 if (fault == NoFault) { 61 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 62 EA, memAccessFlags, &memData); 63 } 64 65 if (fault == NoFault) { 66 %(postacc_code)s; 67 } 68 69 if (fault == NoFault) { 70 %(op_wb)s; 71 } 72 } else { 73 xc->setPredicate(false); 74 } 75 76 if (fault == NoFault && machInst.itstateMask != 0) { 77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 78 } 79 80 return fault; 81 } 82}}; 83 84def template SwapInitiateAcc {{ 85 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 86 Trace::InstRecord *traceData) const 87 { 88 Addr EA; 89 Fault fault = NoFault; 90 91 %(op_decl)s; 92 uint64_t memData = 0; 93 %(op_rd)s; 94 %(ea_code)s; 95 96 if (%(predicate_test)s) 97 { 98 %(preacc_code)s; 99 100 if (fault == NoFault) { 101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 102 memAccessFlags, &memData); 103 } 104 105 if (fault == NoFault) { 106 %(op_wb)s; 107 } 108 } else { 109 xc->setPredicate(false); 110 } 111 112 if (fault == NoFault && machInst.itstateMask != 0) { 113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 114 } 115 116 return fault; 117 } 118}}; 119 120def template SwapCompleteAcc {{ 121 Fault %(class_name)s::completeAcc(PacketPtr pkt, 122 %(CPU_exec_context)s *xc, 123 Trace::InstRecord *traceData) const 124 { 125 Fault fault = NoFault; 126 127 %(op_decl)s; 128 %(op_rd)s; 129 130 if (%(predicate_test)s) 131 { 132 // ARM instructions will not have a pkt if the predicate is false 133 uint64_t memData = pkt->get<typeof(Mem)>(); 134 135 %(postacc_code)s; 136 137 if (fault == NoFault) { 138 %(op_wb)s; 139 } 140 } 141 142 if (fault == NoFault && machInst.itstateMask != 0) { 143 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 144 } 145 146 return fault; 147 } 148}}; 149 150def template LoadExecute {{ 151 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 152 Trace::InstRecord *traceData) const 153 { 154 Addr EA; 155 Fault fault = NoFault; 156 157 %(op_decl)s; 158 %(op_rd)s; 159 %(ea_code)s; 160 161 if (%(predicate_test)s) 162 { 163 if (fault == NoFault) { 164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 165 %(memacc_code)s; 166 } 167 168 if (fault == NoFault) { 169 %(op_wb)s; 170 } 171 } else { 172 xc->setPredicate(false); 173 } 174 175 if (fault == NoFault && machInst.itstateMask != 0) { 176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 177 } 178 179 return fault; 180 } 181}}; 182
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43 44def template SwapExecute {{ 45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 46 Trace::InstRecord *traceData) const 47 { 48 Addr EA; 49 Fault fault = NoFault; 50 51 %(op_decl)s; 52 uint64_t memData = 0; 53 %(op_rd)s; 54 %(ea_code)s; 55 56 if (%(predicate_test)s) 57 { 58 %(preacc_code)s; 59 60 if (fault == NoFault) { 61 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, 62 EA, memAccessFlags, &memData); 63 } 64 65 if (fault == NoFault) { 66 %(postacc_code)s; 67 } 68 69 if (fault == NoFault) { 70 %(op_wb)s; 71 } 72 } else { 73 xc->setPredicate(false); 74 } 75 76 if (fault == NoFault && machInst.itstateMask != 0) { 77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 78 } 79 80 return fault; 81 } 82}}; 83 84def template SwapInitiateAcc {{ 85 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 86 Trace::InstRecord *traceData) const 87 { 88 Addr EA; 89 Fault fault = NoFault; 90 91 %(op_decl)s; 92 uint64_t memData = 0; 93 %(op_rd)s; 94 %(ea_code)s; 95 96 if (%(predicate_test)s) 97 { 98 %(preacc_code)s; 99 100 if (fault == NoFault) { 101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 102 memAccessFlags, &memData); 103 } 104 105 if (fault == NoFault) { 106 %(op_wb)s; 107 } 108 } else { 109 xc->setPredicate(false); 110 } 111 112 if (fault == NoFault && machInst.itstateMask != 0) { 113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 114 } 115 116 return fault; 117 } 118}}; 119 120def template SwapCompleteAcc {{ 121 Fault %(class_name)s::completeAcc(PacketPtr pkt, 122 %(CPU_exec_context)s *xc, 123 Trace::InstRecord *traceData) const 124 { 125 Fault fault = NoFault; 126 127 %(op_decl)s; 128 %(op_rd)s; 129 130 if (%(predicate_test)s) 131 { 132 // ARM instructions will not have a pkt if the predicate is false 133 uint64_t memData = pkt->get<typeof(Mem)>(); 134 135 %(postacc_code)s; 136 137 if (fault == NoFault) { 138 %(op_wb)s; 139 } 140 } 141 142 if (fault == NoFault && machInst.itstateMask != 0) { 143 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 144 } 145 146 return fault; 147 } 148}}; 149 150def template LoadExecute {{ 151 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 152 Trace::InstRecord *traceData) const 153 { 154 Addr EA; 155 Fault fault = NoFault; 156 157 %(op_decl)s; 158 %(op_rd)s; 159 %(ea_code)s; 160 161 if (%(predicate_test)s) 162 { 163 if (fault == NoFault) { 164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 165 %(memacc_code)s; 166 } 167 168 if (fault == NoFault) { 169 %(op_wb)s; 170 } 171 } else { 172 xc->setPredicate(false); 173 } 174 175 if (fault == NoFault && machInst.itstateMask != 0) { 176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 177 } 178 179 return fault; 180 } 181}}; 182
|
423def template StoreExCompleteAcc {{ 424 Fault %(class_name)s::completeAcc(PacketPtr pkt, 425 %(CPU_exec_context)s *xc, 426 Trace::InstRecord *traceData) const 427 { 428 Fault fault = NoFault; 429 430 %(op_decl)s; 431 %(op_rd)s; 432 433 if (%(predicate_test)s) 434 { 435 uint64_t writeResult = pkt->req->getExtraData(); 436 %(postacc_code)s; 437 438 if (fault == NoFault) { 439 %(op_wb)s; 440 } 441 } 442 443 if (fault == NoFault && machInst.itstateMask != 0) { 444 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 445 } 446 447 return fault; 448 } 449}}; 450 451def template RfeDeclare {{ 452 /** 453 * Static instruction class for "%(mnemonic)s". 454 */ 455 class %(class_name)s : public %(base_class)s 456 { 457 public: 458 459 /// Constructor. 460 %(class_name)s(ExtMachInst machInst, 461 uint32_t _base, int _mode, bool _wb); 462 463 %(BasicExecDeclare)s 464 465 %(InitiateAccDeclare)s 466 467 %(CompleteAccDeclare)s 468 }; 469}}; 470 471def template SrsDeclare {{ 472 /** 473 * Static instruction class for "%(mnemonic)s". 474 */ 475 class %(class_name)s : public %(base_class)s 476 { 477 public: 478 479 /// Constructor. 480 %(class_name)s(ExtMachInst machInst, 481 uint32_t _regMode, int _mode, bool _wb); 482 483 %(BasicExecDeclare)s 484 485 %(InitiateAccDeclare)s 486 487 %(CompleteAccDeclare)s 488 }; 489}}; 490 491def template SwapDeclare {{ 492 /** 493 * Static instruction class for "%(mnemonic)s". 494 */ 495 class %(class_name)s : public %(base_class)s 496 { 497 public: 498 499 /// Constructor. 500 %(class_name)s(ExtMachInst machInst, 501 uint32_t _dest, uint32_t _op1, uint32_t _base); 502 503 %(BasicExecDeclare)s 504 505 %(InitiateAccDeclare)s 506 507 %(CompleteAccDeclare)s 508 }; 509}}; 510 511def template LoadStoreDImmDeclare {{ 512 /** 513 * Static instruction class for "%(mnemonic)s". 514 */ 515 class %(class_name)s : public %(base_class)s 516 { 517 public: 518 519 /// Constructor. 520 %(class_name)s(ExtMachInst machInst, 521 uint32_t _dest, uint32_t _dest2, 522 uint32_t _base, bool _add, int32_t _imm); 523 524 %(BasicExecDeclare)s 525 526 %(InitiateAccDeclare)s 527 528 %(CompleteAccDeclare)s 529 }; 530}}; 531 532def template StoreExDImmDeclare {{ 533 /** 534 * Static instruction class for "%(mnemonic)s". 535 */ 536 class %(class_name)s : public %(base_class)s 537 { 538 public: 539 540 /// Constructor. 541 %(class_name)s(ExtMachInst machInst, 542 uint32_t _result, uint32_t _dest, uint32_t _dest2, 543 uint32_t _base, bool _add, int32_t _imm); 544 545 %(BasicExecDeclare)s 546 547 %(InitiateAccDeclare)s 548 549 %(CompleteAccDeclare)s 550 }; 551}}; 552 553def template LoadStoreImmDeclare {{ 554 /** 555 * Static instruction class for "%(mnemonic)s". 556 */ 557 class %(class_name)s : public %(base_class)s 558 { 559 public: 560 561 /// Constructor. 562 %(class_name)s(ExtMachInst machInst, 563 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 564 565 %(BasicExecDeclare)s 566 567 %(InitiateAccDeclare)s 568 569 %(CompleteAccDeclare)s 570 }; 571}}; 572 573def template StoreExImmDeclare {{ 574 /** 575 * Static instruction class for "%(mnemonic)s". 576 */ 577 class %(class_name)s : public %(base_class)s 578 { 579 public: 580 581 /// Constructor. 582 %(class_name)s(ExtMachInst machInst, 583 uint32_t _result, uint32_t _dest, uint32_t _base, 584 bool _add, int32_t _imm); 585 586 %(BasicExecDeclare)s 587 588 %(InitiateAccDeclare)s 589 590 %(CompleteAccDeclare)s 591 }; 592}}; 593 594def template LoadStoreDRegDeclare {{ 595 /** 596 * Static instruction class for "%(mnemonic)s". 597 */ 598 class %(class_name)s : public %(base_class)s 599 { 600 public: 601 602 /// Constructor. 603 %(class_name)s(ExtMachInst machInst, 604 uint32_t _dest, uint32_t _dest2, 605 uint32_t _base, bool _add, 606 int32_t _shiftAmt, uint32_t _shiftType, 607 uint32_t _index); 608 609 %(BasicExecDeclare)s 610 611 %(InitiateAccDeclare)s 612 613 %(CompleteAccDeclare)s 614 }; 615}}; 616 617def template LoadStoreRegDeclare {{ 618 /** 619 * Static instruction class for "%(mnemonic)s". 620 */ 621 class %(class_name)s : public %(base_class)s 622 { 623 public: 624 625 /// Constructor. 626 %(class_name)s(ExtMachInst machInst, 627 uint32_t _dest, uint32_t _base, bool _add, 628 int32_t _shiftAmt, uint32_t _shiftType, 629 uint32_t _index); 630 631 %(BasicExecDeclare)s 632 633 %(InitiateAccDeclare)s 634 635 %(CompleteAccDeclare)s 636 }; 637}}; 638 639def template InitiateAccDeclare {{ 640 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 641}}; 642 643def template CompleteAccDeclare {{ 644 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 645}}; 646 647def template RfeConstructor {{ 648 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 649 uint32_t _base, int _mode, bool _wb) 650 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 651 (IntRegIndex)_base, (AddrMode)_mode, _wb) 652 { 653 %(constructor)s; 654 } 655}}; 656 657def template SrsConstructor {{ 658 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 659 uint32_t _regMode, int _mode, bool _wb) 660 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 661 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 662 { 663 %(constructor)s; 664 } 665}}; 666 667def template SwapConstructor {{ 668 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 669 uint32_t _dest, uint32_t _op1, uint32_t _base) 670 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 671 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 672 { 673 %(constructor)s; 674 } 675}}; 676 677def template LoadStoreDImmConstructor {{ 678 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 679 uint32_t _dest, uint32_t _dest2, 680 uint32_t _base, bool _add, int32_t _imm) 681 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 682 (IntRegIndex)_dest, (IntRegIndex)_dest2, 683 (IntRegIndex)_base, _add, _imm) 684 { 685 %(constructor)s; 686 } 687}}; 688 689def template StoreExDImmConstructor {{ 690 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 691 uint32_t _result, uint32_t _dest, uint32_t _dest2, 692 uint32_t _base, bool _add, int32_t _imm) 693 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 694 (IntRegIndex)_result, 695 (IntRegIndex)_dest, (IntRegIndex)_dest2, 696 (IntRegIndex)_base, _add, _imm) 697 { 698 %(constructor)s; 699 } 700}}; 701 702def template LoadStoreImmConstructor {{ 703 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 704 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 705 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 706 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 707 { 708 %(constructor)s; 709 } 710}}; 711 712def template StoreExImmConstructor {{ 713 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 714 uint32_t _result, uint32_t _dest, uint32_t _base, 715 bool _add, int32_t _imm) 716 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 717 (IntRegIndex)_result, (IntRegIndex)_dest, 718 (IntRegIndex)_base, _add, _imm) 719 { 720 %(constructor)s; 721 } 722}}; 723 724def template LoadStoreDRegConstructor {{ 725 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 726 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 727 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 728 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 729 (IntRegIndex)_dest, (IntRegIndex)_dest2, 730 (IntRegIndex)_base, _add, 731 _shiftAmt, (ArmShiftType)_shiftType, 732 (IntRegIndex)_index) 733 { 734 %(constructor)s; 735 } 736}}; 737 738def template LoadStoreRegConstructor {{ 739 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 740 uint32_t _dest, uint32_t _base, bool _add, 741 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 742 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 743 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 744 _shiftAmt, (ArmShiftType)_shiftType, 745 (IntRegIndex)_index) 746 { 747 %(constructor)s; 748 } 749}};
| 623def template StoreExCompleteAcc {{ 624 Fault %(class_name)s::completeAcc(PacketPtr pkt, 625 %(CPU_exec_context)s *xc, 626 Trace::InstRecord *traceData) const 627 { 628 Fault fault = NoFault; 629 630 %(op_decl)s; 631 %(op_rd)s; 632 633 if (%(predicate_test)s) 634 { 635 uint64_t writeResult = pkt->req->getExtraData(); 636 %(postacc_code)s; 637 638 if (fault == NoFault) { 639 %(op_wb)s; 640 } 641 } 642 643 if (fault == NoFault && machInst.itstateMask != 0) { 644 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 645 } 646 647 return fault; 648 } 649}}; 650 651def template RfeDeclare {{ 652 /** 653 * Static instruction class for "%(mnemonic)s". 654 */ 655 class %(class_name)s : public %(base_class)s 656 { 657 public: 658 659 /// Constructor. 660 %(class_name)s(ExtMachInst machInst, 661 uint32_t _base, int _mode, bool _wb); 662 663 %(BasicExecDeclare)s 664 665 %(InitiateAccDeclare)s 666 667 %(CompleteAccDeclare)s 668 }; 669}}; 670 671def template SrsDeclare {{ 672 /** 673 * Static instruction class for "%(mnemonic)s". 674 */ 675 class %(class_name)s : public %(base_class)s 676 { 677 public: 678 679 /// Constructor. 680 %(class_name)s(ExtMachInst machInst, 681 uint32_t _regMode, int _mode, bool _wb); 682 683 %(BasicExecDeclare)s 684 685 %(InitiateAccDeclare)s 686 687 %(CompleteAccDeclare)s 688 }; 689}}; 690 691def template SwapDeclare {{ 692 /** 693 * Static instruction class for "%(mnemonic)s". 694 */ 695 class %(class_name)s : public %(base_class)s 696 { 697 public: 698 699 /// Constructor. 700 %(class_name)s(ExtMachInst machInst, 701 uint32_t _dest, uint32_t _op1, uint32_t _base); 702 703 %(BasicExecDeclare)s 704 705 %(InitiateAccDeclare)s 706 707 %(CompleteAccDeclare)s 708 }; 709}}; 710 711def template LoadStoreDImmDeclare {{ 712 /** 713 * Static instruction class for "%(mnemonic)s". 714 */ 715 class %(class_name)s : public %(base_class)s 716 { 717 public: 718 719 /// Constructor. 720 %(class_name)s(ExtMachInst machInst, 721 uint32_t _dest, uint32_t _dest2, 722 uint32_t _base, bool _add, int32_t _imm); 723 724 %(BasicExecDeclare)s 725 726 %(InitiateAccDeclare)s 727 728 %(CompleteAccDeclare)s 729 }; 730}}; 731 732def template StoreExDImmDeclare {{ 733 /** 734 * Static instruction class for "%(mnemonic)s". 735 */ 736 class %(class_name)s : public %(base_class)s 737 { 738 public: 739 740 /// Constructor. 741 %(class_name)s(ExtMachInst machInst, 742 uint32_t _result, uint32_t _dest, uint32_t _dest2, 743 uint32_t _base, bool _add, int32_t _imm); 744 745 %(BasicExecDeclare)s 746 747 %(InitiateAccDeclare)s 748 749 %(CompleteAccDeclare)s 750 }; 751}}; 752 753def template LoadStoreImmDeclare {{ 754 /** 755 * Static instruction class for "%(mnemonic)s". 756 */ 757 class %(class_name)s : public %(base_class)s 758 { 759 public: 760 761 /// Constructor. 762 %(class_name)s(ExtMachInst machInst, 763 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 764 765 %(BasicExecDeclare)s 766 767 %(InitiateAccDeclare)s 768 769 %(CompleteAccDeclare)s 770 }; 771}}; 772 773def template StoreExImmDeclare {{ 774 /** 775 * Static instruction class for "%(mnemonic)s". 776 */ 777 class %(class_name)s : public %(base_class)s 778 { 779 public: 780 781 /// Constructor. 782 %(class_name)s(ExtMachInst machInst, 783 uint32_t _result, uint32_t _dest, uint32_t _base, 784 bool _add, int32_t _imm); 785 786 %(BasicExecDeclare)s 787 788 %(InitiateAccDeclare)s 789 790 %(CompleteAccDeclare)s 791 }; 792}}; 793 794def template LoadStoreDRegDeclare {{ 795 /** 796 * Static instruction class for "%(mnemonic)s". 797 */ 798 class %(class_name)s : public %(base_class)s 799 { 800 public: 801 802 /// Constructor. 803 %(class_name)s(ExtMachInst machInst, 804 uint32_t _dest, uint32_t _dest2, 805 uint32_t _base, bool _add, 806 int32_t _shiftAmt, uint32_t _shiftType, 807 uint32_t _index); 808 809 %(BasicExecDeclare)s 810 811 %(InitiateAccDeclare)s 812 813 %(CompleteAccDeclare)s 814 }; 815}}; 816 817def template LoadStoreRegDeclare {{ 818 /** 819 * Static instruction class for "%(mnemonic)s". 820 */ 821 class %(class_name)s : public %(base_class)s 822 { 823 public: 824 825 /// Constructor. 826 %(class_name)s(ExtMachInst machInst, 827 uint32_t _dest, uint32_t _base, bool _add, 828 int32_t _shiftAmt, uint32_t _shiftType, 829 uint32_t _index); 830 831 %(BasicExecDeclare)s 832 833 %(InitiateAccDeclare)s 834 835 %(CompleteAccDeclare)s 836 }; 837}}; 838 839def template InitiateAccDeclare {{ 840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 841}}; 842 843def template CompleteAccDeclare {{ 844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 845}}; 846 847def template RfeConstructor {{ 848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 849 uint32_t _base, int _mode, bool _wb) 850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 851 (IntRegIndex)_base, (AddrMode)_mode, _wb) 852 { 853 %(constructor)s; 854 } 855}}; 856 857def template SrsConstructor {{ 858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 859 uint32_t _regMode, int _mode, bool _wb) 860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 861 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 862 { 863 %(constructor)s; 864 } 865}}; 866 867def template SwapConstructor {{ 868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 869 uint32_t _dest, uint32_t _op1, uint32_t _base) 870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 872 { 873 %(constructor)s; 874 } 875}}; 876 877def template LoadStoreDImmConstructor {{ 878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 879 uint32_t _dest, uint32_t _dest2, 880 uint32_t _base, bool _add, int32_t _imm) 881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 882 (IntRegIndex)_dest, (IntRegIndex)_dest2, 883 (IntRegIndex)_base, _add, _imm) 884 { 885 %(constructor)s; 886 } 887}}; 888 889def template StoreExDImmConstructor {{ 890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 891 uint32_t _result, uint32_t _dest, uint32_t _dest2, 892 uint32_t _base, bool _add, int32_t _imm) 893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 894 (IntRegIndex)_result, 895 (IntRegIndex)_dest, (IntRegIndex)_dest2, 896 (IntRegIndex)_base, _add, _imm) 897 { 898 %(constructor)s; 899 } 900}}; 901 902def template LoadStoreImmConstructor {{ 903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 907 { 908 %(constructor)s; 909 } 910}}; 911 912def template StoreExImmConstructor {{ 913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 914 uint32_t _result, uint32_t _dest, uint32_t _base, 915 bool _add, int32_t _imm) 916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 917 (IntRegIndex)_result, (IntRegIndex)_dest, 918 (IntRegIndex)_base, _add, _imm) 919 { 920 %(constructor)s; 921 } 922}}; 923 924def template LoadStoreDRegConstructor {{ 925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 929 (IntRegIndex)_dest, (IntRegIndex)_dest2, 930 (IntRegIndex)_base, _add, 931 _shiftAmt, (ArmShiftType)_shiftType, 932 (IntRegIndex)_index) 933 { 934 %(constructor)s; 935 } 936}}; 937 938def template LoadStoreRegConstructor {{ 939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 940 uint32_t _dest, uint32_t _base, bool _add, 941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 943 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 944 _shiftAmt, (ArmShiftType)_shiftType, 945 (IntRegIndex)_index) 946 { 947 %(constructor)s; 948 } 949}};
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