347 } 348 349 return fault; 350 } 351}}; 352 353def template LoadCompleteAcc {{ 354 Fault %(class_name)s::completeAcc(PacketPtr pkt, 355 %(CPU_exec_context)s *xc, 356 Trace::InstRecord *traceData) const 357 { 358 Fault fault = NoFault; 359 360 %(op_decl)s; 361 %(op_rd)s; 362 363 if (%(predicate_test)s) 364 { 365 // ARM instructions will not have a pkt if the predicate is false 366 Mem = pkt->get<typeof(Mem)>(); 367 368 if (fault == NoFault) { 369 %(memacc_code)s; 370 } 371 372 if (fault == NoFault) { 373 %(op_wb)s; 374 } 375 } 376 377 if (fault == NoFault && machInst.itstateMask != 0) { 378 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 379 } 380 381 return fault; 382 } 383}}; 384 385def template StoreCompleteAcc {{ 386 Fault %(class_name)s::completeAcc(PacketPtr pkt, 387 %(CPU_exec_context)s *xc, 388 Trace::InstRecord *traceData) const 389 { 390 Fault fault = NoFault; 391 392 %(op_decl)s; 393 %(op_rd)s; 394 395 if (%(predicate_test)s) 396 { 397 if (fault == NoFault) { 398 %(op_wb)s; 399 } 400 } 401 402 if (fault == NoFault && machInst.itstateMask != 0) { 403 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 404 } 405 406 return fault; 407 } 408}}; 409 410def template StoreExCompleteAcc {{ 411 Fault %(class_name)s::completeAcc(PacketPtr pkt, 412 %(CPU_exec_context)s *xc, 413 Trace::InstRecord *traceData) const 414 { 415 Fault fault = NoFault; 416 417 %(op_decl)s; 418 %(op_rd)s; 419 420 if (%(predicate_test)s) 421 { 422 uint64_t writeResult = pkt->req->getExtraData(); 423 %(postacc_code)s; 424 425 if (fault == NoFault) { 426 %(op_wb)s; 427 } 428 } 429 430 if (fault == NoFault && machInst.itstateMask != 0) { 431 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 432 } 433 434 return fault; 435 } 436}}; 437 438def template RfeDeclare {{ 439 /** 440 * Static instruction class for "%(mnemonic)s". 441 */ 442 class %(class_name)s : public %(base_class)s 443 { 444 public: 445 446 /// Constructor. 447 %(class_name)s(ExtMachInst machInst, 448 uint32_t _base, int _mode, bool _wb); 449 450 %(BasicExecDeclare)s 451 452 %(InitiateAccDeclare)s 453 454 %(CompleteAccDeclare)s 455 }; 456}}; 457 458def template SrsDeclare {{ 459 /** 460 * Static instruction class for "%(mnemonic)s". 461 */ 462 class %(class_name)s : public %(base_class)s 463 { 464 public: 465 466 /// Constructor. 467 %(class_name)s(ExtMachInst machInst, 468 uint32_t _regMode, int _mode, bool _wb); 469 470 %(BasicExecDeclare)s 471 472 %(InitiateAccDeclare)s 473 474 %(CompleteAccDeclare)s 475 }; 476}}; 477 478def template SwapDeclare {{ 479 /** 480 * Static instruction class for "%(mnemonic)s". 481 */ 482 class %(class_name)s : public %(base_class)s 483 { 484 public: 485 486 /// Constructor. 487 %(class_name)s(ExtMachInst machInst, 488 uint32_t _dest, uint32_t _op1, uint32_t _base); 489 490 %(BasicExecDeclare)s 491 492 %(InitiateAccDeclare)s 493 494 %(CompleteAccDeclare)s 495 }; 496}}; 497 498def template LoadStoreDImmDeclare {{ 499 /** 500 * Static instruction class for "%(mnemonic)s". 501 */ 502 class %(class_name)s : public %(base_class)s 503 { 504 public: 505 506 /// Constructor. 507 %(class_name)s(ExtMachInst machInst, 508 uint32_t _dest, uint32_t _dest2, 509 uint32_t _base, bool _add, int32_t _imm); 510 511 %(BasicExecDeclare)s 512 513 %(InitiateAccDeclare)s 514 515 %(CompleteAccDeclare)s 516 }; 517}}; 518 519def template StoreExDImmDeclare {{ 520 /** 521 * Static instruction class for "%(mnemonic)s". 522 */ 523 class %(class_name)s : public %(base_class)s 524 { 525 public: 526 527 /// Constructor. 528 %(class_name)s(ExtMachInst machInst, 529 uint32_t _result, uint32_t _dest, uint32_t _dest2, 530 uint32_t _base, bool _add, int32_t _imm); 531 532 %(BasicExecDeclare)s 533 534 %(InitiateAccDeclare)s 535 536 %(CompleteAccDeclare)s 537 }; 538}}; 539 540def template LoadStoreImmDeclare {{ 541 /** 542 * Static instruction class for "%(mnemonic)s". 543 */ 544 class %(class_name)s : public %(base_class)s 545 { 546 public: 547 548 /// Constructor. 549 %(class_name)s(ExtMachInst machInst, 550 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 551 552 %(BasicExecDeclare)s 553 554 %(InitiateAccDeclare)s 555 556 %(CompleteAccDeclare)s 557 }; 558}}; 559 560def template StoreExImmDeclare {{ 561 /** 562 * Static instruction class for "%(mnemonic)s". 563 */ 564 class %(class_name)s : public %(base_class)s 565 { 566 public: 567 568 /// Constructor. 569 %(class_name)s(ExtMachInst machInst, 570 uint32_t _result, uint32_t _dest, uint32_t _base, 571 bool _add, int32_t _imm); 572 573 %(BasicExecDeclare)s 574 575 %(InitiateAccDeclare)s 576 577 %(CompleteAccDeclare)s 578 }; 579}}; 580 581def template LoadStoreDRegDeclare {{ 582 /** 583 * Static instruction class for "%(mnemonic)s". 584 */ 585 class %(class_name)s : public %(base_class)s 586 { 587 public: 588 589 /// Constructor. 590 %(class_name)s(ExtMachInst machInst, 591 uint32_t _dest, uint32_t _dest2, 592 uint32_t _base, bool _add, 593 int32_t _shiftAmt, uint32_t _shiftType, 594 uint32_t _index); 595 596 %(BasicExecDeclare)s 597 598 %(InitiateAccDeclare)s 599 600 %(CompleteAccDeclare)s 601 }; 602}}; 603 604def template LoadStoreRegDeclare {{ 605 /** 606 * Static instruction class for "%(mnemonic)s". 607 */ 608 class %(class_name)s : public %(base_class)s 609 { 610 public: 611 612 /// Constructor. 613 %(class_name)s(ExtMachInst machInst, 614 uint32_t _dest, uint32_t _base, bool _add, 615 int32_t _shiftAmt, uint32_t _shiftType, 616 uint32_t _index); 617 618 %(BasicExecDeclare)s 619 620 %(InitiateAccDeclare)s 621 622 %(CompleteAccDeclare)s 623 }; 624}}; 625 626def template InitiateAccDeclare {{ 627 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 628}}; 629 630def template CompleteAccDeclare {{ 631 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 632}}; 633 634def template RfeConstructor {{ 635 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 636 uint32_t _base, int _mode, bool _wb) 637 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 638 (IntRegIndex)_base, (AddrMode)_mode, _wb) 639 { 640 %(constructor)s; 641 } 642}}; 643 644def template SrsConstructor {{ 645 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 646 uint32_t _regMode, int _mode, bool _wb) 647 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 648 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 649 { 650 %(constructor)s; 651 } 652}}; 653 654def template SwapConstructor {{ 655 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 656 uint32_t _dest, uint32_t _op1, uint32_t _base) 657 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 658 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 659 { 660 %(constructor)s; 661 } 662}}; 663 664def template LoadStoreDImmConstructor {{ 665 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 666 uint32_t _dest, uint32_t _dest2, 667 uint32_t _base, bool _add, int32_t _imm) 668 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 669 (IntRegIndex)_dest, (IntRegIndex)_dest2, 670 (IntRegIndex)_base, _add, _imm) 671 { 672 %(constructor)s; 673 } 674}}; 675 676def template StoreExDImmConstructor {{ 677 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 678 uint32_t _result, uint32_t _dest, uint32_t _dest2, 679 uint32_t _base, bool _add, int32_t _imm) 680 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 681 (IntRegIndex)_result, 682 (IntRegIndex)_dest, (IntRegIndex)_dest2, 683 (IntRegIndex)_base, _add, _imm) 684 { 685 %(constructor)s; 686 } 687}}; 688 689def template LoadStoreImmConstructor {{ 690 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 691 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 692 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 693 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 694 { 695 %(constructor)s; 696 } 697}}; 698 699def template StoreExImmConstructor {{ 700 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 701 uint32_t _result, uint32_t _dest, uint32_t _base, 702 bool _add, int32_t _imm) 703 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 704 (IntRegIndex)_result, (IntRegIndex)_dest, 705 (IntRegIndex)_base, _add, _imm) 706 { 707 %(constructor)s; 708 } 709}}; 710 711def template LoadStoreDRegConstructor {{ 712 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 713 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 714 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 715 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 716 (IntRegIndex)_dest, (IntRegIndex)_dest2, 717 (IntRegIndex)_base, _add, 718 _shiftAmt, (ArmShiftType)_shiftType, 719 (IntRegIndex)_index) 720 { 721 %(constructor)s; 722 } 723}}; 724 725def template LoadStoreRegConstructor {{ 726 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 727 uint32_t _dest, uint32_t _base, bool _add, 728 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 729 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 730 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 731 _shiftAmt, (ArmShiftType)_shiftType, 732 (IntRegIndex)_index) 733 { 734 %(constructor)s; 735 } 736}};
| 364 } 365 366 return fault; 367 } 368}}; 369 370def template LoadCompleteAcc {{ 371 Fault %(class_name)s::completeAcc(PacketPtr pkt, 372 %(CPU_exec_context)s *xc, 373 Trace::InstRecord *traceData) const 374 { 375 Fault fault = NoFault; 376 377 %(op_decl)s; 378 %(op_rd)s; 379 380 if (%(predicate_test)s) 381 { 382 // ARM instructions will not have a pkt if the predicate is false 383 Mem = pkt->get<typeof(Mem)>(); 384 385 if (fault == NoFault) { 386 %(memacc_code)s; 387 } 388 389 if (fault == NoFault) { 390 %(op_wb)s; 391 } 392 } 393 394 if (fault == NoFault && machInst.itstateMask != 0) { 395 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 396 } 397 398 return fault; 399 } 400}}; 401 402def template StoreCompleteAcc {{ 403 Fault %(class_name)s::completeAcc(PacketPtr pkt, 404 %(CPU_exec_context)s *xc, 405 Trace::InstRecord *traceData) const 406 { 407 Fault fault = NoFault; 408 409 %(op_decl)s; 410 %(op_rd)s; 411 412 if (%(predicate_test)s) 413 { 414 if (fault == NoFault) { 415 %(op_wb)s; 416 } 417 } 418 419 if (fault == NoFault && machInst.itstateMask != 0) { 420 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 421 } 422 423 return fault; 424 } 425}}; 426 427def template StoreExCompleteAcc {{ 428 Fault %(class_name)s::completeAcc(PacketPtr pkt, 429 %(CPU_exec_context)s *xc, 430 Trace::InstRecord *traceData) const 431 { 432 Fault fault = NoFault; 433 434 %(op_decl)s; 435 %(op_rd)s; 436 437 if (%(predicate_test)s) 438 { 439 uint64_t writeResult = pkt->req->getExtraData(); 440 %(postacc_code)s; 441 442 if (fault == NoFault) { 443 %(op_wb)s; 444 } 445 } 446 447 if (fault == NoFault && machInst.itstateMask != 0) { 448 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 449 } 450 451 return fault; 452 } 453}}; 454 455def template RfeDeclare {{ 456 /** 457 * Static instruction class for "%(mnemonic)s". 458 */ 459 class %(class_name)s : public %(base_class)s 460 { 461 public: 462 463 /// Constructor. 464 %(class_name)s(ExtMachInst machInst, 465 uint32_t _base, int _mode, bool _wb); 466 467 %(BasicExecDeclare)s 468 469 %(InitiateAccDeclare)s 470 471 %(CompleteAccDeclare)s 472 }; 473}}; 474 475def template SrsDeclare {{ 476 /** 477 * Static instruction class for "%(mnemonic)s". 478 */ 479 class %(class_name)s : public %(base_class)s 480 { 481 public: 482 483 /// Constructor. 484 %(class_name)s(ExtMachInst machInst, 485 uint32_t _regMode, int _mode, bool _wb); 486 487 %(BasicExecDeclare)s 488 489 %(InitiateAccDeclare)s 490 491 %(CompleteAccDeclare)s 492 }; 493}}; 494 495def template SwapDeclare {{ 496 /** 497 * Static instruction class for "%(mnemonic)s". 498 */ 499 class %(class_name)s : public %(base_class)s 500 { 501 public: 502 503 /// Constructor. 504 %(class_name)s(ExtMachInst machInst, 505 uint32_t _dest, uint32_t _op1, uint32_t _base); 506 507 %(BasicExecDeclare)s 508 509 %(InitiateAccDeclare)s 510 511 %(CompleteAccDeclare)s 512 }; 513}}; 514 515def template LoadStoreDImmDeclare {{ 516 /** 517 * Static instruction class for "%(mnemonic)s". 518 */ 519 class %(class_name)s : public %(base_class)s 520 { 521 public: 522 523 /// Constructor. 524 %(class_name)s(ExtMachInst machInst, 525 uint32_t _dest, uint32_t _dest2, 526 uint32_t _base, bool _add, int32_t _imm); 527 528 %(BasicExecDeclare)s 529 530 %(InitiateAccDeclare)s 531 532 %(CompleteAccDeclare)s 533 }; 534}}; 535 536def template StoreExDImmDeclare {{ 537 /** 538 * Static instruction class for "%(mnemonic)s". 539 */ 540 class %(class_name)s : public %(base_class)s 541 { 542 public: 543 544 /// Constructor. 545 %(class_name)s(ExtMachInst machInst, 546 uint32_t _result, uint32_t _dest, uint32_t _dest2, 547 uint32_t _base, bool _add, int32_t _imm); 548 549 %(BasicExecDeclare)s 550 551 %(InitiateAccDeclare)s 552 553 %(CompleteAccDeclare)s 554 }; 555}}; 556 557def template LoadStoreImmDeclare {{ 558 /** 559 * Static instruction class for "%(mnemonic)s". 560 */ 561 class %(class_name)s : public %(base_class)s 562 { 563 public: 564 565 /// Constructor. 566 %(class_name)s(ExtMachInst machInst, 567 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 568 569 %(BasicExecDeclare)s 570 571 %(InitiateAccDeclare)s 572 573 %(CompleteAccDeclare)s 574 }; 575}}; 576 577def template StoreExImmDeclare {{ 578 /** 579 * Static instruction class for "%(mnemonic)s". 580 */ 581 class %(class_name)s : public %(base_class)s 582 { 583 public: 584 585 /// Constructor. 586 %(class_name)s(ExtMachInst machInst, 587 uint32_t _result, uint32_t _dest, uint32_t _base, 588 bool _add, int32_t _imm); 589 590 %(BasicExecDeclare)s 591 592 %(InitiateAccDeclare)s 593 594 %(CompleteAccDeclare)s 595 }; 596}}; 597 598def template LoadStoreDRegDeclare {{ 599 /** 600 * Static instruction class for "%(mnemonic)s". 601 */ 602 class %(class_name)s : public %(base_class)s 603 { 604 public: 605 606 /// Constructor. 607 %(class_name)s(ExtMachInst machInst, 608 uint32_t _dest, uint32_t _dest2, 609 uint32_t _base, bool _add, 610 int32_t _shiftAmt, uint32_t _shiftType, 611 uint32_t _index); 612 613 %(BasicExecDeclare)s 614 615 %(InitiateAccDeclare)s 616 617 %(CompleteAccDeclare)s 618 }; 619}}; 620 621def template LoadStoreRegDeclare {{ 622 /** 623 * Static instruction class for "%(mnemonic)s". 624 */ 625 class %(class_name)s : public %(base_class)s 626 { 627 public: 628 629 /// Constructor. 630 %(class_name)s(ExtMachInst machInst, 631 uint32_t _dest, uint32_t _base, bool _add, 632 int32_t _shiftAmt, uint32_t _shiftType, 633 uint32_t _index); 634 635 %(BasicExecDeclare)s 636 637 %(InitiateAccDeclare)s 638 639 %(CompleteAccDeclare)s 640 }; 641}}; 642 643def template InitiateAccDeclare {{ 644 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 645}}; 646 647def template CompleteAccDeclare {{ 648 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 649}}; 650 651def template RfeConstructor {{ 652 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 653 uint32_t _base, int _mode, bool _wb) 654 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 655 (IntRegIndex)_base, (AddrMode)_mode, _wb) 656 { 657 %(constructor)s; 658 } 659}}; 660 661def template SrsConstructor {{ 662 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 663 uint32_t _regMode, int _mode, bool _wb) 664 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 665 (OperatingMode)_regMode, (AddrMode)_mode, _wb) 666 { 667 %(constructor)s; 668 } 669}}; 670 671def template SwapConstructor {{ 672 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 673 uint32_t _dest, uint32_t _op1, uint32_t _base) 674 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 675 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 676 { 677 %(constructor)s; 678 } 679}}; 680 681def template LoadStoreDImmConstructor {{ 682 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 683 uint32_t _dest, uint32_t _dest2, 684 uint32_t _base, bool _add, int32_t _imm) 685 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 686 (IntRegIndex)_dest, (IntRegIndex)_dest2, 687 (IntRegIndex)_base, _add, _imm) 688 { 689 %(constructor)s; 690 } 691}}; 692 693def template StoreExDImmConstructor {{ 694 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 695 uint32_t _result, uint32_t _dest, uint32_t _dest2, 696 uint32_t _base, bool _add, int32_t _imm) 697 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 698 (IntRegIndex)_result, 699 (IntRegIndex)_dest, (IntRegIndex)_dest2, 700 (IntRegIndex)_base, _add, _imm) 701 { 702 %(constructor)s; 703 } 704}}; 705 706def template LoadStoreImmConstructor {{ 707 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 708 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 709 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 710 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 711 { 712 %(constructor)s; 713 } 714}}; 715 716def template StoreExImmConstructor {{ 717 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 718 uint32_t _result, uint32_t _dest, uint32_t _base, 719 bool _add, int32_t _imm) 720 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 721 (IntRegIndex)_result, (IntRegIndex)_dest, 722 (IntRegIndex)_base, _add, _imm) 723 { 724 %(constructor)s; 725 } 726}}; 727 728def template LoadStoreDRegConstructor {{ 729 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 730 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 731 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 732 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 733 (IntRegIndex)_dest, (IntRegIndex)_dest2, 734 (IntRegIndex)_base, _add, 735 _shiftAmt, (ArmShiftType)_shiftType, 736 (IntRegIndex)_index) 737 { 738 %(constructor)s; 739 } 740}}; 741 742def template LoadStoreRegConstructor {{ 743 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 744 uint32_t _dest, uint32_t _base, bool _add, 745 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 746 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 747 (IntRegIndex)_dest, (IntRegIndex)_base, _add, 748 _shiftAmt, (ArmShiftType)_shiftType, 749 (IntRegIndex)_index) 750 { 751 %(constructor)s; 752 } 753}};
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