mem.isa (8203:78b9f056d58a) | mem.isa (8205:7ecbffb674aa) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 88 unchanged lines hidden (view full) --- 97 98 if (fault == NoFault) { 99 %(op_wb)s; 100 } 101 } else { 102 xc->setPredicate(false); 103 } 104 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 88 unchanged lines hidden (view full) --- 97 98 if (fault == NoFault) { 99 %(op_wb)s; 100 } 101 } else { 102 xc->setPredicate(false); 103 } 104 |
105 if (fault == NoFault && machInst.itstateMask != 0 && 106 (!isMicroop() || isLastMicroop())) { 107 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 108 } 109 | |
110 return fault; 111 } 112}}; 113 114def template SwapInitiateAcc {{ 115 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 116 Trace::InstRecord *traceData) const 117 { --- 12 unchanged lines hidden (view full) --- 130 if (fault == NoFault) { 131 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 132 memAccessFlags, &memData); 133 } 134 } else { 135 xc->setPredicate(false); 136 } 137 | 105 return fault; 106 } 107}}; 108 109def template SwapInitiateAcc {{ 110 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 111 Trace::InstRecord *traceData) const 112 { --- 12 unchanged lines hidden (view full) --- 125 if (fault == NoFault) { 126 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 127 memAccessFlags, &memData); 128 } 129 } else { 130 xc->setPredicate(false); 131 } 132 |
138 if (fault == NoFault && machInst.itstateMask != 0 && 139 (!isMicroop() || isLastMicroop())) { 140 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 141 } 142 | |
143 return fault; 144 } 145}}; 146 147def template SwapCompleteAcc {{ 148 Fault %(class_name)s::completeAcc(PacketPtr pkt, 149 %(CPU_exec_context)s *xc, 150 Trace::InstRecord *traceData) const --- 10 unchanged lines hidden (view full) --- 161 162 %(postacc_code)s; 163 164 if (fault == NoFault) { 165 %(op_wb)s; 166 } 167 } 168 | 133 return fault; 134 } 135}}; 136 137def template SwapCompleteAcc {{ 138 Fault %(class_name)s::completeAcc(PacketPtr pkt, 139 %(CPU_exec_context)s *xc, 140 Trace::InstRecord *traceData) const --- 10 unchanged lines hidden (view full) --- 151 152 %(postacc_code)s; 153 154 if (fault == NoFault) { 155 %(op_wb)s; 156 } 157 } 158 |
169 if (fault == NoFault && machInst.itstateMask != 0) { 170 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 171 } 172 | |
173 return fault; 174 } 175}}; 176 177def template LoadExecute {{ 178 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 179 Trace::InstRecord *traceData) const 180 { --- 13 unchanged lines hidden (view full) --- 194 195 if (fault == NoFault) { 196 %(op_wb)s; 197 } 198 } else { 199 xc->setPredicate(false); 200 } 201 | 159 return fault; 160 } 161}}; 162 163def template LoadExecute {{ 164 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 165 Trace::InstRecord *traceData) const 166 { --- 13 unchanged lines hidden (view full) --- 180 181 if (fault == NoFault) { 182 %(op_wb)s; 183 } 184 } else { 185 xc->setPredicate(false); 186 } 187 |
202 if (fault == NoFault && machInst.itstateMask != 0 && 203 (!isMicroop() || isLastMicroop())) { 204 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 205 } 206 | |
207 return fault; 208 } 209}}; 210 211def template NeonLoadExecute {{ 212 template <class Element> 213 Fault %(class_name)s<Element>::execute( 214 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 18 unchanged lines hidden (view full) --- 233 234 if (fault == NoFault) { 235 %(op_wb)s; 236 } 237 } else { 238 xc->setPredicate(false); 239 } 240 | 188 return fault; 189 } 190}}; 191 192def template NeonLoadExecute {{ 193 template <class Element> 194 Fault %(class_name)s<Element>::execute( 195 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 18 unchanged lines hidden (view full) --- 214 215 if (fault == NoFault) { 216 %(op_wb)s; 217 } 218 } else { 219 xc->setPredicate(false); 220 } 221 |
241 if (fault == NoFault && machInst.itstateMask != 0 && 242 (!isMicroop() || isLastMicroop())) { 243 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 244 } 245 | |
246 return fault; 247 } 248}}; 249 250def template StoreExecute {{ 251 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 252 Trace::InstRecord *traceData) const 253 { --- 17 unchanged lines hidden (view full) --- 271 272 if (fault == NoFault) { 273 %(op_wb)s; 274 } 275 } else { 276 xc->setPredicate(false); 277 } 278 | 222 return fault; 223 } 224}}; 225 226def template StoreExecute {{ 227 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 228 Trace::InstRecord *traceData) const 229 { --- 17 unchanged lines hidden (view full) --- 247 248 if (fault == NoFault) { 249 %(op_wb)s; 250 } 251 } else { 252 xc->setPredicate(false); 253 } 254 |
279 if (fault == NoFault && machInst.itstateMask != 0 && 280 (!isMicroop() || isLastMicroop())) { 281 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 282 } 283 | |
284 return fault; 285 } 286}}; 287 288def template NeonStoreExecute {{ 289 template <class Element> 290 Fault %(class_name)s<Element>::execute( 291 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 22 unchanged lines hidden (view full) --- 314 315 if (fault == NoFault) { 316 %(op_wb)s; 317 } 318 } else { 319 xc->setPredicate(false); 320 } 321 | 255 return fault; 256 } 257}}; 258 259def template NeonStoreExecute {{ 260 template <class Element> 261 Fault %(class_name)s<Element>::execute( 262 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 22 unchanged lines hidden (view full) --- 285 286 if (fault == NoFault) { 287 %(op_wb)s; 288 } 289 } else { 290 xc->setPredicate(false); 291 } 292 |
322 if (fault == NoFault && machInst.itstateMask != 0 && 323 (!isMicroop() || isLastMicroop())) { 324 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 325 } 326 | |
327 return fault; 328 } 329}}; 330 331def template StoreExExecute {{ 332 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 333 Trace::InstRecord *traceData) const 334 { --- 23 unchanged lines hidden (view full) --- 358 359 if (fault == NoFault) { 360 %(op_wb)s; 361 } 362 } else { 363 xc->setPredicate(false); 364 } 365 | 293 return fault; 294 } 295}}; 296 297def template StoreExExecute {{ 298 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 299 Trace::InstRecord *traceData) const 300 { --- 23 unchanged lines hidden (view full) --- 324 325 if (fault == NoFault) { 326 %(op_wb)s; 327 } 328 } else { 329 xc->setPredicate(false); 330 } 331 |
366 if (fault == NoFault && machInst.itstateMask != 0 && 367 (!isMicroop() || isLastMicroop())) { 368 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 369 } 370 | |
371 return fault; 372 } 373}}; 374 375def template StoreExInitiateAcc {{ 376 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 377 Trace::InstRecord *traceData) const 378 { --- 12 unchanged lines hidden (view full) --- 391 392 if (fault == NoFault) { 393 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 394 memAccessFlags, NULL); 395 } 396 } else { 397 xc->setPredicate(false); 398 } | 332 return fault; 333 } 334}}; 335 336def template StoreExInitiateAcc {{ 337 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 338 Trace::InstRecord *traceData) const 339 { --- 12 unchanged lines hidden (view full) --- 352 353 if (fault == NoFault) { 354 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 355 memAccessFlags, NULL); 356 } 357 } else { 358 xc->setPredicate(false); 359 } |
399 if (fault == NoFault && machInst.itstateMask != 0 && 400 (!isMicroop() || isLastMicroop())) { 401 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 402 } | |
403 404 return fault; 405 } 406}}; 407 408def template StoreInitiateAcc {{ 409 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 410 Trace::InstRecord *traceData) const --- 14 unchanged lines hidden (view full) --- 425 if (fault == NoFault) { 426 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 427 memAccessFlags, NULL); 428 } 429 } else { 430 xc->setPredicate(false); 431 } 432 | 360 361 return fault; 362 } 363}}; 364 365def template StoreInitiateAcc {{ 366 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 367 Trace::InstRecord *traceData) const --- 14 unchanged lines hidden (view full) --- 382 if (fault == NoFault) { 383 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 384 memAccessFlags, NULL); 385 } 386 } else { 387 xc->setPredicate(false); 388 } 389 |
433 if (fault == NoFault && machInst.itstateMask != 0 && 434 (!isMicroop() || isLastMicroop())) { 435 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 436 } 437 | |
438 return fault; 439 } 440}}; 441 442def template NeonStoreInitiateAcc {{ 443 template <class Element> 444 Fault %(class_name)s<Element>::initiateAcc( 445 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 16 unchanged lines hidden (view full) --- 462 if (fault == NoFault) { 463 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 464 memAccessFlags, NULL); 465 } 466 } else { 467 xc->setPredicate(false); 468 } 469 | 390 return fault; 391 } 392}}; 393 394def template NeonStoreInitiateAcc {{ 395 template <class Element> 396 Fault %(class_name)s<Element>::initiateAcc( 397 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const --- 16 unchanged lines hidden (view full) --- 414 if (fault == NoFault) { 415 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA, 416 memAccessFlags, NULL); 417 } 418 } else { 419 xc->setPredicate(false); 420 } 421 |
470 if (fault == NoFault && machInst.itstateMask != 0 && 471 (!isMicroop() || isLastMicroop())) { 472 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 473 } 474 | |
475 return fault; 476 } 477}}; 478 479def template LoadInitiateAcc {{ 480 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 481 Trace::InstRecord *traceData) const 482 { --- 6 unchanged lines hidden (view full) --- 489 490 if (%(predicate_test)s) 491 { 492 if (fault == NoFault) { 493 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 494 } 495 } else { 496 xc->setPredicate(false); | 422 return fault; 423 } 424}}; 425 426def template LoadInitiateAcc {{ 427 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 428 Trace::InstRecord *traceData) const 429 { --- 6 unchanged lines hidden (view full) --- 436 437 if (%(predicate_test)s) 438 { 439 if (fault == NoFault) { 440 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 441 } 442 } else { 443 xc->setPredicate(false); |
497 if (fault == NoFault && machInst.itstateMask != 0 && 498 (!isMicroop() || isLastMicroop())) { 499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 500 } | |
501 } 502 503 return fault; 504 } 505}}; 506 507def template NeonLoadInitiateAcc {{ 508 template <class Element> --- 9 unchanged lines hidden (view full) --- 518 519 if (%(predicate_test)s) 520 { 521 if (fault == NoFault) { 522 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 523 } 524 } else { 525 xc->setPredicate(false); | 444 } 445 446 return fault; 447 } 448}}; 449 450def template NeonLoadInitiateAcc {{ 451 template <class Element> --- 9 unchanged lines hidden (view full) --- 461 462 if (%(predicate_test)s) 463 { 464 if (fault == NoFault) { 465 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags); 466 } 467 } else { 468 xc->setPredicate(false); |
526 if (fault == NoFault && machInst.itstateMask != 0 && 527 (!isMicroop() || isLastMicroop())) { 528 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 529 } | |
530 } 531 532 return fault; 533 } 534}}; 535 536def template LoadCompleteAcc {{ 537 Fault %(class_name)s::completeAcc(PacketPtr pkt, --- 14 unchanged lines hidden (view full) --- 552 %(memacc_code)s; 553 } 554 555 if (fault == NoFault) { 556 %(op_wb)s; 557 } 558 } 559 | 469 } 470 471 return fault; 472 } 473}}; 474 475def template LoadCompleteAcc {{ 476 Fault %(class_name)s::completeAcc(PacketPtr pkt, --- 14 unchanged lines hidden (view full) --- 491 %(memacc_code)s; 492 } 493 494 if (fault == NoFault) { 495 %(op_wb)s; 496 } 497 } 498 |
560 if (fault == NoFault && machInst.itstateMask != 0) { 561 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 562 } 563 | |
564 return fault; 565 } 566}}; 567 568def template NeonLoadCompleteAcc {{ 569 template <class Element> 570 Fault %(class_name)s<Element>::completeAcc( 571 PacketPtr pkt, %(CPU_exec_context)s *xc, --- 14 unchanged lines hidden (view full) --- 586 %(memacc_code)s; 587 } 588 589 if (fault == NoFault) { 590 %(op_wb)s; 591 } 592 } 593 | 499 return fault; 500 } 501}}; 502 503def template NeonLoadCompleteAcc {{ 504 template <class Element> 505 Fault %(class_name)s<Element>::completeAcc( 506 PacketPtr pkt, %(CPU_exec_context)s *xc, --- 14 unchanged lines hidden (view full) --- 521 %(memacc_code)s; 522 } 523 524 if (fault == NoFault) { 525 %(op_wb)s; 526 } 527 } 528 |
594 if (fault == NoFault && machInst.itstateMask != 0) { 595 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 596 } 597 | |
598 return fault; 599 } 600}}; 601 602def template StoreCompleteAcc {{ 603 Fault %(class_name)s::completeAcc(PacketPtr pkt, 604 %(CPU_exec_context)s *xc, 605 Trace::InstRecord *traceData) const 606 { | 529 return fault; 530 } 531}}; 532 533def template StoreCompleteAcc {{ 534 Fault %(class_name)s::completeAcc(PacketPtr pkt, 535 %(CPU_exec_context)s *xc, 536 Trace::InstRecord *traceData) const 537 { |
607 if (machInst.itstateMask != 0) { 608 warn_once("Complete acc isn't called on normal stores in O3."); 609 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 610 } | |
611 return NoFault; 612 } 613}}; 614 615def template NeonStoreCompleteAcc {{ 616 template <class Element> 617 Fault %(class_name)s<Element>::completeAcc( 618 PacketPtr pkt, %(CPU_exec_context)s *xc, 619 Trace::InstRecord *traceData) const 620 { | 538 return NoFault; 539 } 540}}; 541 542def template NeonStoreCompleteAcc {{ 543 template <class Element> 544 Fault %(class_name)s<Element>::completeAcc( 545 PacketPtr pkt, %(CPU_exec_context)s *xc, 546 Trace::InstRecord *traceData) const 547 { |
621 if (machInst.itstateMask != 0) { 622 warn_once("Complete acc isn't called on normal stores in O3."); 623 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 624 } | |
625 return NoFault; 626 } 627}}; 628 629def template StoreExCompleteAcc {{ 630 Fault %(class_name)s::completeAcc(PacketPtr pkt, 631 %(CPU_exec_context)s *xc, 632 Trace::InstRecord *traceData) const --- 8 unchanged lines hidden (view full) --- 641 uint64_t writeResult = pkt->req->getExtraData(); 642 %(postacc_code)s; 643 644 if (fault == NoFault) { 645 %(op_wb)s; 646 } 647 } 648 | 548 return NoFault; 549 } 550}}; 551 552def template StoreExCompleteAcc {{ 553 Fault %(class_name)s::completeAcc(PacketPtr pkt, 554 %(CPU_exec_context)s *xc, 555 Trace::InstRecord *traceData) const --- 8 unchanged lines hidden (view full) --- 564 uint64_t writeResult = pkt->req->getExtraData(); 565 %(postacc_code)s; 566 567 if (fault == NoFault) { 568 %(op_wb)s; 569 } 570 } 571 |
649 if (fault == NoFault && machInst.itstateMask != 0) { 650 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 651 } 652 | |
653 return fault; 654 } 655}}; 656 657def template RfeDeclare {{ 658 /** 659 * Static instruction class for "%(mnemonic)s". 660 */ --- 620 unchanged lines hidden --- | 572 return fault; 573 } 574}}; 575 576def template RfeDeclare {{ 577 /** 578 * Static instruction class for "%(mnemonic)s". 579 */ --- 620 unchanged lines hidden --- |