mem.isa (7291:2d21be52e57f) | mem.isa (7303:6b70985664c8) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 176 unchanged lines hidden (view full) --- 185 %(op_wb)s; 186 } 187 } 188 189 return fault; 190 } 191}}; 192 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 176 unchanged lines hidden (view full) --- 185 %(op_wb)s; 186 } 187 } 188 189 return fault; 190 } 191}}; 192 |
193def template StoreExExecute {{ 194 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 195 Trace::InstRecord *traceData) const 196 { 197 Addr EA; 198 Fault fault = NoFault; 199 200 %(op_decl)s; 201 %(op_rd)s; 202 %(ea_code)s; 203 204 if (%(predicate_test)s) 205 { 206 if (fault == NoFault) { 207 %(memacc_code)s; 208 } 209 210 uint64_t writeResult; 211 212 if (fault == NoFault) { 213 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 214 memAccessFlags, &writeResult); 215 if (traceData) { traceData->setData(Mem); } 216 } 217 218 if (fault == NoFault) { 219 %(postacc_code)s; 220 } 221 222 if (fault == NoFault) { 223 %(op_wb)s; 224 } 225 } 226 227 return fault; 228 } 229}}; 230 231def template StoreExInitiateAcc {{ 232 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 233 Trace::InstRecord *traceData) const 234 { 235 Addr EA; 236 Fault fault = NoFault; 237 238 %(op_decl)s; 239 %(op_rd)s; 240 %(ea_code)s; 241 242 if (%(predicate_test)s) 243 { 244 if (fault == NoFault) { 245 %(memacc_code)s; 246 } 247 248 if (fault == NoFault) { 249 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 250 memAccessFlags, NULL); 251 if (traceData) { traceData->setData(Mem); } 252 } 253 254 // Need to write back any potential address register update 255 if (fault == NoFault) { 256 %(op_wb)s; 257 } 258 } 259 260 return fault; 261 } 262}}; 263 |
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193def template StoreInitiateAcc {{ 194 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 195 Trace::InstRecord *traceData) const 196 { 197 Addr EA; 198 Fault fault = NoFault; 199 200 %(op_decl)s; --- 88 unchanged lines hidden (view full) --- 289 %(op_wb)s; 290 } 291 } 292 293 return fault; 294 } 295}}; 296 | 264def template StoreInitiateAcc {{ 265 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 266 Trace::InstRecord *traceData) const 267 { 268 Addr EA; 269 Fault fault = NoFault; 270 271 %(op_decl)s; --- 88 unchanged lines hidden (view full) --- 360 %(op_wb)s; 361 } 362 } 363 364 return fault; 365 } 366}}; 367 |
368def template StoreExCompleteAcc {{ 369 Fault %(class_name)s::completeAcc(PacketPtr pkt, 370 %(CPU_exec_context)s *xc, 371 Trace::InstRecord *traceData) const 372 { 373 Fault fault = NoFault; 374 375 %(op_decl)s; 376 %(op_rd)s; 377 378 if (%(predicate_test)s) 379 { 380 uint64_t writeResult = pkt->req->getExtraData(); 381 %(postacc_code)s; 382 383 if (fault == NoFault) { 384 %(op_wb)s; 385 } 386 } 387 388 return fault; 389 } 390}}; 391 |
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297def template RfeDeclare {{ 298 /** 299 * Static instruction class for "%(mnemonic)s". 300 */ 301 class %(class_name)s : public %(base_class)s 302 { 303 public: 304 --- 45 unchanged lines hidden (view full) --- 350 %(BasicExecDeclare)s 351 352 %(InitiateAccDeclare)s 353 354 %(CompleteAccDeclare)s 355 }; 356}}; 357 | 392def template RfeDeclare {{ 393 /** 394 * Static instruction class for "%(mnemonic)s". 395 */ 396 class %(class_name)s : public %(base_class)s 397 { 398 public: 399 --- 45 unchanged lines hidden (view full) --- 445 %(BasicExecDeclare)s 446 447 %(InitiateAccDeclare)s 448 449 %(CompleteAccDeclare)s 450 }; 451}}; 452 |
453def template StoreExDImmDeclare {{ 454 /** 455 * Static instruction class for "%(mnemonic)s". 456 */ 457 class %(class_name)s : public %(base_class)s 458 { 459 public: 460 461 /// Constructor. 462 %(class_name)s(ExtMachInst machInst, 463 uint32_t _result, uint32_t _dest, uint32_t _dest2, 464 uint32_t _base, bool _add, int32_t _imm); 465 466 %(BasicExecDeclare)s 467 468 %(InitiateAccDeclare)s 469 470 %(CompleteAccDeclare)s 471 }; 472}}; 473 |
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358def template LoadStoreImmDeclare {{ 359 /** 360 * Static instruction class for "%(mnemonic)s". 361 */ 362 class %(class_name)s : public %(base_class)s 363 { 364 public: 365 --- 4 unchanged lines hidden (view full) --- 370 %(BasicExecDeclare)s 371 372 %(InitiateAccDeclare)s 373 374 %(CompleteAccDeclare)s 375 }; 376}}; 377 | 474def template LoadStoreImmDeclare {{ 475 /** 476 * Static instruction class for "%(mnemonic)s". 477 */ 478 class %(class_name)s : public %(base_class)s 479 { 480 public: 481 --- 4 unchanged lines hidden (view full) --- 486 %(BasicExecDeclare)s 487 488 %(InitiateAccDeclare)s 489 490 %(CompleteAccDeclare)s 491 }; 492}}; 493 |
494def template StoreExImmDeclare {{ 495 /** 496 * Static instruction class for "%(mnemonic)s". 497 */ 498 class %(class_name)s : public %(base_class)s 499 { 500 public: 501 502 /// Constructor. 503 %(class_name)s(ExtMachInst machInst, 504 uint32_t _result, uint32_t _dest, uint32_t _base, 505 bool _add, int32_t _imm); 506 507 %(BasicExecDeclare)s 508 509 %(InitiateAccDeclare)s 510 511 %(CompleteAccDeclare)s 512 }; 513}}; 514 |
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378def template LoadStoreDRegDeclare {{ 379 /** 380 * Static instruction class for "%(mnemonic)s". 381 */ 382 class %(class_name)s : public %(base_class)s 383 { 384 public: 385 --- 69 unchanged lines hidden (view full) --- 455 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 456 (IntRegIndex)_dest, (IntRegIndex)_dest2, 457 (IntRegIndex)_base, _add, _imm) 458 { 459 %(constructor)s; 460 } 461}}; 462 | 515def template LoadStoreDRegDeclare {{ 516 /** 517 * Static instruction class for "%(mnemonic)s". 518 */ 519 class %(class_name)s : public %(base_class)s 520 { 521 public: 522 --- 69 unchanged lines hidden (view full) --- 592 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 593 (IntRegIndex)_dest, (IntRegIndex)_dest2, 594 (IntRegIndex)_base, _add, _imm) 595 { 596 %(constructor)s; 597 } 598}}; 599 |
600def template StoreExDImmConstructor {{ 601 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 602 uint32_t _result, uint32_t _dest, uint32_t _dest2, 603 uint32_t _base, bool _add, int32_t _imm) 604 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 605 (IntRegIndex)_result, 606 (IntRegIndex)_dest, (IntRegIndex)_dest2, 607 (IntRegIndex)_base, _add, _imm) 608 { 609 %(constructor)s; 610 } 611}}; 612 |
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463def template LoadStoreImmConstructor {{ 464 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 465 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 466 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 467 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 468 { 469 %(constructor)s; 470 } 471}}; 472 | 613def template LoadStoreImmConstructor {{ 614 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 615 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 616 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 617 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 618 { 619 %(constructor)s; 620 } 621}}; 622 |
623def template StoreExImmConstructor {{ 624 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 625 uint32_t _result, uint32_t _dest, uint32_t _base, 626 bool _add, int32_t _imm) 627 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 628 (IntRegIndex)_result, (IntRegIndex)_dest, 629 (IntRegIndex)_base, _add, _imm) 630 { 631 %(constructor)s; 632 } 633}}; 634 |
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473def template LoadStoreDRegConstructor {{ 474 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 475 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 476 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 477 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 478 (IntRegIndex)_dest, (IntRegIndex)_dest2, 479 (IntRegIndex)_base, _add, 480 _shiftAmt, (ArmShiftType)_shiftType, --- 18 unchanged lines hidden --- | 635def template LoadStoreDRegConstructor {{ 636 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 637 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 638 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 639 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 640 (IntRegIndex)_dest, (IntRegIndex)_dest2, 641 (IntRegIndex)_base, _add, 642 _shiftAmt, (ArmShiftType)_shiftType, --- 18 unchanged lines hidden --- |