1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30
31
32def template LoadExecute {{
33 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
34 Trace::InstRecord *traceData) const
35 {
36 Addr EA;
37 Fault fault = NoFault;
38
39 %(op_decl)s;
40 %(op_rd)s;
41 %(ea_code)s;
42
43 if (%(predicate_test)s)
44 {
45 if (fault == NoFault) {
46 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
47 %(memacc_code)s;
48 }
49
50 if (fault == NoFault) {
51 %(op_wb)s;
52 }
53 }
54
55 return fault;
56 }
57}};
58
59def template LoadInitiateAcc {{
60 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
61 Trace::InstRecord *traceData) const
62 {
63 Addr EA;
64 Fault fault = NoFault;
65
66 %(op_src_decl)s;
67 %(op_rd)s;
68 %(ea_code)s;
69
70 if (%(predicate_test)s)
71 {
72 if (fault == NoFault) {
73 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
74 }
75 }
76
77 return fault;
78 }
79}};
80
81def template LoadCompleteAcc {{
82 Fault %(class_name)s::completeAcc(PacketPtr pkt,
83 %(CPU_exec_context)s *xc,
84 Trace::InstRecord *traceData) const
85 {
86 Fault fault = NoFault;
87
88 %(op_decl)s;
89 %(op_rd)s;
90
91 if (%(predicate_test)s)
92 {
93 // ARM instructions will not have a pkt if the predicate is false
94 Mem = pkt->get<typeof(Mem)>();
95
96 if (fault == NoFault) {
97 %(memacc_code)s;
98 }
99
100 if (fault == NoFault) {
101 %(op_wb)s;
102 }
103 }
104
105 return fault;
106 }
107}};
108
109def template LoadStoreImmDeclare {{
110 /**
111 * Static instruction class for "%(mnemonic)s".
112 */
113 class %(class_name)s : public %(base_class)s
114 {
115 public:
116
117 /// Constructor.
118 %(class_name)s(ExtMachInst machInst,
119 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
120
121 %(BasicExecDeclare)s
122
123 %(InitiateAccDeclare)s
124
125 %(CompleteAccDeclare)s
126 };
127}};
128
129def template LoadStoreRegDeclare {{
130 /**
131 * Static instruction class for "%(mnemonic)s".
132 */
133 class %(class_name)s : public %(base_class)s
134 {
135 public:
136
137 /// Constructor.
138 %(class_name)s(ExtMachInst machInst,
139 uint32_t _dest, uint32_t _base, bool _add,
140 int32_t _shiftAmt, uint32_t _shiftType,
141 uint32_t _index);
142
143 %(BasicExecDeclare)s
144
145 %(InitiateAccDeclare)s
146
147 %(CompleteAccDeclare)s
148 };
149}};
150
151def template InitiateAccDeclare {{
152 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
153}};
154
155def template CompleteAccDeclare {{
156 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
157}};
158
159def template LoadStoreImmConstructor {{
160 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
161 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
162 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
163 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
164 {
165 %(constructor)s;
166 }
167}};
168
169def template LoadStoreRegConstructor {{
170 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
171 uint32_t _dest, uint32_t _base, bool _add,
172 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
173 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
174 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
175 _shiftAmt, (ArmShiftType)_shiftType,
176 (IntRegIndex)_index)
177 {
178 %(constructor)s;
179 }
180}};