1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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908
909def template RfeConstructor {{
910 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
911 uint32_t _base, int _mode, bool _wb)
912 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
913 (IntRegIndex)_base, (AddrMode)_mode, _wb)
914 {
915 %(constructor)s;
916#if %(use_uops)d
917 assert(numMicroops >= 2);
918 uops = new StaticInstPtr[numMicroops];
919 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
920 uops[0]->setDelayedCommit();
921 uops[1] = new %(wb_decl)s;
922 uops[1]->setLastMicroop();
923#endif
924 }
925}};
926
927def template SrsConstructor {{
928 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
929 uint32_t _regMode, int _mode, bool _wb)
930 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
931 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
932 {
933 %(constructor)s;
934#if %(use_uops)d
935 assert(numMicroops >= 2);
936 uops = new StaticInstPtr[numMicroops];
937 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
938 uops[0]->setDelayedCommit();
939 uops[1] = new %(wb_decl)s;
940 uops[1]->setLastMicroop();
941#endif
942 }
943}};
944
945def template SwapConstructor {{
946 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
947 uint32_t _dest, uint32_t _op1, uint32_t _base)
948 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
949 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
950 {
951 %(constructor)s;
952 }
953}};
954
955def template LoadStoreDImmConstructor {{
956 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
957 uint32_t _dest, uint32_t _dest2,
958 uint32_t _base, bool _add, int32_t _imm)
959 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
960 (IntRegIndex)_dest, (IntRegIndex)_dest2,
961 (IntRegIndex)_base, _add, _imm)
962 {
963 %(constructor)s;
964#if %(use_uops)d
965 assert(numMicroops >= 2);
966 uops = new StaticInstPtr[numMicroops];
967 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
968 uops[0]->setDelayedCommit();
969 uops[1] = new %(wb_decl)s;
970 uops[1]->setLastMicroop();
971#endif

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977 uint32_t _result, uint32_t _dest, uint32_t _dest2,
978 uint32_t _base, bool _add, int32_t _imm)
979 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
980 (IntRegIndex)_result,
981 (IntRegIndex)_dest, (IntRegIndex)_dest2,
982 (IntRegIndex)_base, _add, _imm)
983 {
984 %(constructor)s;
985#if %(use_uops)d
986 assert(numMicroops >= 2);
987 uops = new StaticInstPtr[numMicroops];
988 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
989 _base, _add, _imm);
990 uops[0]->setDelayedCommit();
991 uops[1] = new %(wb_decl)s;
992 uops[1]->setLastMicroop();
993#endif
994 }
995}};
996
997def template LoadStoreImmConstructor {{
998 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
999 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1000 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1001 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1002 {
1003 %(constructor)s;
1004#if %(use_uops)d
1005 assert(numMicroops >= 2);
1006 uops = new StaticInstPtr[numMicroops];
1007 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1008 uops[0]->setDelayedCommit();
1009 uops[1] = new %(wb_decl)s;
1010 uops[1]->setLastMicroop();
1011#endif

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1016 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1017 uint32_t _result, uint32_t _dest, uint32_t _base,
1018 bool _add, int32_t _imm)
1019 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1020 (IntRegIndex)_result, (IntRegIndex)_dest,
1021 (IntRegIndex)_base, _add, _imm)
1022 {
1023 %(constructor)s;
1024#if %(use_uops)d
1025 assert(numMicroops >= 2);
1026 uops = new StaticInstPtr[numMicroops];
1027 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1028 _base, _add, _imm);
1029 uops[0]->setDelayedCommit();
1030 uops[1] = new %(wb_decl)s;
1031 uops[1]->setLastMicroop();

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1039 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1040 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1041 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1042 (IntRegIndex)_base, _add,
1043 _shiftAmt, (ArmShiftType)_shiftType,
1044 (IntRegIndex)_index)
1045 {
1046 %(constructor)s;
1047#if %(use_uops)d
1048 assert(numMicroops >= 2);
1049 uops = new StaticInstPtr[numMicroops];
1050 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1051 _shiftAmt, _shiftType, _index);
1052 uops[0]->setDelayedCommit();
1053 uops[1] = new %(wb_decl)s;
1054 uops[1]->setLastMicroop();

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1061 uint32_t _dest, uint32_t _base, bool _add,
1062 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1063 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1064 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1065 _shiftAmt, (ArmShiftType)_shiftType,
1066 (IntRegIndex)_index)
1067 {
1068 %(constructor)s;
1069#if %(use_uops)d
1070 assert(numMicroops >= 2);
1071 uops = new StaticInstPtr[numMicroops];
1072 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1073 _shiftAmt, _shiftType, _index);
1074 uops[0]->setDelayedCommit();
1075 uops[1] = new %(wb_decl)s;
1076 uops[1]->setLastMicroop();

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1084 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1085 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1086 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1087 (IntRegIndex)_base, _add,
1088 _shiftAmt, (ArmShiftType)_shiftType,
1089 (IntRegIndex)_index)
1090 {
1091 %(constructor)s;
1092#if %(use_uops)d
1093 assert(numMicroops >= 2);
1094 uops = new StaticInstPtr[numMicroops];
1095 if ((_dest == _index) || (_dest2 == _index)) {
1096 IntRegIndex wbIndexReg = INTREG_UREG0;
1097 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1098 uops[0]->setDelayedCommit();
1099 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,

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1118 uint32_t _dest, uint32_t _base, bool _add,
1119 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1121 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1122 _shiftAmt, (ArmShiftType)_shiftType,
1123 (IntRegIndex)_index)
1124 {
1125 %(constructor)s;
1126#if %(use_uops)d
1127 assert(numMicroops >= 2);
1128 uops = new StaticInstPtr[numMicroops];
1129 if (_dest == INTREG_PC) {
1130 IntRegIndex wbIndexReg = index;
1131 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1132 _shiftAmt, _shiftType, _index);
1133 uops[0]->setDelayedCommit();

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1159
1160def template LoadImmConstructor {{
1161 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1162 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1163 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1164 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1165 {
1166 %(constructor)s;
1167#if %(use_uops)d
1168 assert(numMicroops >= 2);
1169 uops = new StaticInstPtr[numMicroops];
1170 if (_dest == INTREG_PC) {
1171 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1172 _imm);
1173 uops[0]->setDelayedCommit();
1174 uops[1] = new %(wb_decl)s;

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