1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template SwapExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;

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68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 } else {
73 xc->setPredicate(false);
74 }
75
76 if (fault == NoFault && machInst.itstateMask != 0) {
77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
78 }
79
80 return fault;
81 }
82}};
83
84def template SwapInitiateAcc {{

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104
105 if (fault == NoFault) {
106 %(op_wb)s;
107 }
108 } else {
109 xc->setPredicate(false);
110 }
111
112 if (fault == NoFault && machInst.itstateMask != 0) {
113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
114 }
115
116 return fault;
117 }
118}};
119
120def template SwapCompleteAcc {{

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167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 } else {
172 xc->setPredicate(false);
173 }
174
175 if (fault == NoFault && machInst.itstateMask != 0) {
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }
181}};
182
183def template NeonLoadExecute {{

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203 %(memacc_code)s;
204 }
205
206 if (fault == NoFault) {
207 %(op_wb)s;
208 }
209 }
210
211 if (fault == NoFault && machInst.itstateMask != 0) {
212 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
213 }
214
215 return fault;
216 }
217}};
218
219def template StoreExecute {{

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240
241 if (fault == NoFault) {
242 %(op_wb)s;
243 }
244 } else {
245 xc->setPredicate(false);
246 }
247
248 if (fault == NoFault && machInst.itstateMask != 0) {
249 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
250 }
251
252 return fault;
253 }
254}};
255
256def template NeonStoreExecute {{

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280 memAccessFlags, NULL);
281 }
282
283 if (fault == NoFault) {
284 %(op_wb)s;
285 }
286 }
287
288 if (fault == NoFault && machInst.itstateMask != 0) {
289 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
290 }
291
292 return fault;
293 }
294}};
295
296def template StoreExExecute {{

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323
324 if (fault == NoFault) {
325 %(op_wb)s;
326 }
327 } else {
328 xc->setPredicate(false);
329 }
330
331 if (fault == NoFault && machInst.itstateMask != 0) {
332 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
333 }
334
335 return fault;
336 }
337}};
338
339def template StoreExInitiateAcc {{

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360
361 // Need to write back any potential address register update
362 if (fault == NoFault) {
363 %(op_wb)s;
364 }
365 } else {
366 xc->setPredicate(false);
367 }
368
369 if (fault == NoFault && machInst.itstateMask != 0) {
370 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
371 }
372
373 return fault;
374 }
375}};
376
377def template StoreInitiateAcc {{

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399 // Need to write back any potential address register update
400 if (fault == NoFault) {
401 %(op_wb)s;
402 }
403 } else {
404 xc->setPredicate(false);
405 }
406
407 if (fault == NoFault && machInst.itstateMask != 0) {
408 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
409 }
410
411 return fault;
412 }
413}};
414
415def template NeonStoreInitiateAcc {{

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438 }
439
440 // Need to write back any potential address register update
441 if (fault == NoFault) {
442 %(op_wb)s;
443 }
444 }
445
446 if (fault == NoFault && machInst.itstateMask != 0) {
447 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
448 }
449
450 return fault;
451 }
452}};
453
454def template LoadInitiateAcc {{

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464
465 if (%(predicate_test)s)
466 {
467 if (fault == NoFault) {
468 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
469 }
470 } else {
471 xc->setPredicate(false);
472 if (fault == NoFault && machInst.itstateMask != 0) {
473 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
474 }
475 }
476
477 return fault;
478 }
479}};
480

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490 %(op_rd)s;
491 %(ea_code)s;
492
493 if (%(predicate_test)s)
494 {
495 if (fault == NoFault) {
496 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
497 }
498 } else if (fault == NoFault && machInst.itstateMask != 0) {
499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
500 }
501
502 return fault;
503 }
504}};
505
506def template LoadCompleteAcc {{

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786 %(BasicExecDeclare)s
787
788 %(InitiateAccDeclare)s
789
790 %(CompleteAccDeclare)s
791 };
792}};
793
794def template LoadStoreDRegDeclare {{
795 /**
796 * Static instruction class for "%(mnemonic)s".
797 */
798 class %(class_name)s : public %(base_class)s
799 {
800 public:
801
802 /// Constructor.

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809 %(BasicExecDeclare)s
810
811 %(InitiateAccDeclare)s
812
813 %(CompleteAccDeclare)s
814 };
815}};
816
817def template LoadStoreRegDeclare {{
818 /**
819 * Static instruction class for "%(mnemonic)s".
820 */
821 class %(class_name)s : public %(base_class)s
822 {
823 public:
824
825 /// Constructor.

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831 %(BasicExecDeclare)s
832
833 %(InitiateAccDeclare)s
834
835 %(CompleteAccDeclare)s
836 };
837}};
838
839def template InitiateAccDeclare {{
840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
841}};
842
843def template CompleteAccDeclare {{
844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
845}};
846
847def template RfeConstructor {{
848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 uint32_t _base, int _mode, bool _wb)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 (IntRegIndex)_base, (AddrMode)_mode, _wb)
852 {
853 %(constructor)s;
854 }
855}};
856
857def template SrsConstructor {{
858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
859 uint32_t _regMode, int _mode, bool _wb)
860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
861 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
862 {
863 %(constructor)s;
864 }
865}};
866
867def template SwapConstructor {{
868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
869 uint32_t _dest, uint32_t _op1, uint32_t _base)
870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)

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878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
879 uint32_t _dest, uint32_t _dest2,
880 uint32_t _base, bool _add, int32_t _imm)
881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
882 (IntRegIndex)_dest, (IntRegIndex)_dest2,
883 (IntRegIndex)_base, _add, _imm)
884 {
885 %(constructor)s;
886 }
887}};
888
889def template StoreExDImmConstructor {{
890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
891 uint32_t _result, uint32_t _dest, uint32_t _dest2,
892 uint32_t _base, bool _add, int32_t _imm)
893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
894 (IntRegIndex)_result,
895 (IntRegIndex)_dest, (IntRegIndex)_dest2,
896 (IntRegIndex)_base, _add, _imm)
897 {
898 %(constructor)s;
899 }
900}};
901
902def template LoadStoreImmConstructor {{
903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
907 {
908 %(constructor)s;
909 }
910}};
911
912def template StoreExImmConstructor {{
913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
914 uint32_t _result, uint32_t _dest, uint32_t _base,
915 bool _add, int32_t _imm)
916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
917 (IntRegIndex)_result, (IntRegIndex)_dest,
918 (IntRegIndex)_base, _add, _imm)
919 {
920 %(constructor)s;
921 }
922}};
923
924def template LoadStoreDRegConstructor {{
925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
929 (IntRegIndex)_dest, (IntRegIndex)_dest2,
930 (IntRegIndex)_base, _add,
931 _shiftAmt, (ArmShiftType)_shiftType,
932 (IntRegIndex)_index)
933 {
934 %(constructor)s;
935 }
936}};
937
938def template LoadStoreRegConstructor {{
939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
940 uint32_t _dest, uint32_t _base, bool _add,
941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
943 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
944 _shiftAmt, (ArmShiftType)_shiftType,
945 (IntRegIndex)_index)
946 {
947 %(constructor)s;
948 }
949}};