1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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175 if (fault == NoFault && machInst.itstateMask != 0) {
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }
181}};
182
183def template StoreExecute {{
184 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
185 Trace::InstRecord *traceData) const
186 {
187 Addr EA;
188 Fault fault = NoFault;
189
190 %(op_decl)s;

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212 if (fault == NoFault && machInst.itstateMask != 0) {
213 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
214 }
215
216 return fault;
217 }
218}};
219
220def template StoreExExecute {{
221 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
222 Trace::InstRecord *traceData) const
223 {
224 Addr EA;
225 Fault fault = NoFault;
226
227 %(op_decl)s;

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331 if (fault == NoFault && machInst.itstateMask != 0) {
332 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
333 }
334
335 return fault;
336 }
337}};
338
339def template LoadInitiateAcc {{
340 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
341 Trace::InstRecord *traceData) const
342 {
343 Addr EA;
344 Fault fault = NoFault;
345
346 %(op_src_decl)s;

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358 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
359 }
360 }
361
362 return fault;
363 }
364}};
365
366def template LoadCompleteAcc {{
367 Fault %(class_name)s::completeAcc(PacketPtr pkt,
368 %(CPU_exec_context)s *xc,
369 Trace::InstRecord *traceData) const
370 {
371 Fault fault = NoFault;
372
373 %(op_decl)s;

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390 if (fault == NoFault && machInst.itstateMask != 0) {
391 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
392 }
393
394 return fault;
395 }
396}};
397
398def template StoreCompleteAcc {{
399 Fault %(class_name)s::completeAcc(PacketPtr pkt,
400 %(CPU_exec_context)s *xc,
401 Trace::InstRecord *traceData) const
402 {
403 Fault fault = NoFault;
404
405 %(op_decl)s;

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415 if (fault == NoFault && machInst.itstateMask != 0) {
416 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
417 }
418
419 return fault;
420 }
421}};
422
423def template StoreExCompleteAcc {{
424 Fault %(class_name)s::completeAcc(PacketPtr pkt,
425 %(CPU_exec_context)s *xc,
426 Trace::InstRecord *traceData) const
427 {
428 Fault fault = NoFault;
429
430 %(op_decl)s;

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