1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 }
73
74 if (fault == NoFault && machInst.itstateMask != 0) {
75 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
76 }
77
78 return fault;
79 }

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98 if (fault == NoFault) {
99 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
100 memAccessFlags, &memData);
101 }
102
103 if (fault == NoFault) {
104 %(op_wb)s;
105 }
106 }
107
108 if (fault == NoFault && machInst.itstateMask != 0) {
109 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
110 }
111
112 return fault;
113 }

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159 if (fault == NoFault) {
160 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
161 %(memacc_code)s;
162 }
163
164 if (fault == NoFault) {
165 %(op_wb)s;
166 }
167 }
168
169 if (fault == NoFault && machInst.itstateMask != 0) {
170 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
171 }
172
173 return fault;
174 }

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195 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
196 memAccessFlags, NULL);
197 if (traceData) { traceData->setData(Mem); }
198 }
199
200 if (fault == NoFault) {
201 %(op_wb)s;
202 }
203 }
204
205 if (fault == NoFault && machInst.itstateMask != 0) {
206 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
207 }
208
209 return fault;
210 }

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237
238 if (fault == NoFault) {
239 %(postacc_code)s;
240 }
241
242 if (fault == NoFault) {
243 %(op_wb)s;
244 }
245 }
246
247 if (fault == NoFault && machInst.itstateMask != 0) {
248 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
249 }
250
251 return fault;
252 }

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274 memAccessFlags, NULL);
275 if (traceData) { traceData->setData(Mem); }
276 }
277
278 // Need to write back any potential address register update
279 if (fault == NoFault) {
280 %(op_wb)s;
281 }
282 }
283
284 if (fault == NoFault && machInst.itstateMask != 0) {
285 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
286 }
287
288 return fault;
289 }

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311 memAccessFlags, NULL);
312 if (traceData) { traceData->setData(Mem); }
313 }
314
315 // Need to write back any potential address register update
316 if (fault == NoFault) {
317 %(op_wb)s;
318 }
319 }
320
321 if (fault == NoFault && machInst.itstateMask != 0) {
322 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
323 }
324
325 return fault;
326 }

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337 %(op_rd)s;
338 %(ea_code)s;
339
340 if (%(predicate_test)s)
341 {
342 if (fault == NoFault) {
343 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
344 }
345 } else if (fault == NoFault && machInst.itstateMask != 0) {
346 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
347 }
348
349 return fault;
350 }
351}};
352
353def template LoadCompleteAcc {{
354 Fault %(class_name)s::completeAcc(PacketPtr pkt,

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