1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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185 %(op_wb)s;
186 }
187 }
188
189 return fault;
190 }
191}};
192
193def template StoreInitiateAcc {{
194 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
195 Trace::InstRecord *traceData) const
196 {
197 Addr EA;
198 Fault fault = NoFault;
199
200 %(op_decl)s;

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289 %(op_wb)s;
290 }
291 }
292
293 return fault;
294 }
295}};
296
297def template RfeDeclare {{
298 /**
299 * Static instruction class for "%(mnemonic)s".
300 */
301 class %(class_name)s : public %(base_class)s
302 {
303 public:
304

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350 %(BasicExecDeclare)s
351
352 %(InitiateAccDeclare)s
353
354 %(CompleteAccDeclare)s
355 };
356}};
357
358def template LoadStoreImmDeclare {{
359 /**
360 * Static instruction class for "%(mnemonic)s".
361 */
362 class %(class_name)s : public %(base_class)s
363 {
364 public:
365

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370 %(BasicExecDeclare)s
371
372 %(InitiateAccDeclare)s
373
374 %(CompleteAccDeclare)s
375 };
376}};
377
378def template LoadStoreDRegDeclare {{
379 /**
380 * Static instruction class for "%(mnemonic)s".
381 */
382 class %(class_name)s : public %(base_class)s
383 {
384 public:
385

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455 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
456 (IntRegIndex)_dest, (IntRegIndex)_dest2,
457 (IntRegIndex)_base, _add, _imm)
458 {
459 %(constructor)s;
460 }
461}};
462
463def template LoadStoreImmConstructor {{
464 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
465 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
466 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
467 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
468 {
469 %(constructor)s;
470 }
471}};
472
473def template LoadStoreDRegConstructor {{
474 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
475 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
476 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
477 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
478 (IntRegIndex)_dest, (IntRegIndex)_dest2,
479 (IntRegIndex)_base, _add,
480 _shiftAmt, (ArmShiftType)_shiftType,

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