1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template LoadExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;

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199 %(op_wb)s;
200 }
201 }
202
203 return fault;
204 }
205}};
206
207def template LoadStoreImmDeclare {{
208 /**
209 * Static instruction class for "%(mnemonic)s".
210 */
211 class %(class_name)s : public %(base_class)s
212 {
213 public:
214

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249def template InitiateAccDeclare {{
250 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
251}};
252
253def template CompleteAccDeclare {{
254 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
255}};
256
257def template LoadStoreImmConstructor {{
258 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
259 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
260 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
261 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
262 {
263 %(constructor)s;
264 }

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