1// -*- mode:c++ -*-
2
3// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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577 class %(class_name)s : public %(base_class)s
578 {
579 public:
580
581 /// Constructor.
582 %(class_name)s(ExtMachInst machInst,
583 uint32_t _base, int _mode, bool _wb);
584
585 %(BasicExecDeclare)s
586
587 %(InitiateAccDeclare)s
588
589 %(CompleteAccDeclare)s
590 };
591}};
592
593def template SrsDeclare {{
594 /**
595 * Static instruction class for "%(mnemonic)s".
596 */
597 class %(class_name)s : public %(base_class)s
598 {
599 public:
600
601 /// Constructor.
602 %(class_name)s(ExtMachInst machInst,
603 uint32_t _regMode, int _mode, bool _wb);
604
605 %(BasicExecDeclare)s
606
607 %(InitiateAccDeclare)s
608
609 %(CompleteAccDeclare)s
610 };
611}};
612
613def template SwapDeclare {{
614 /**
615 * Static instruction class for "%(mnemonic)s".
616 */
617 class %(class_name)s : public %(base_class)s
618 {
619 public:
620
621 /// Constructor.
622 %(class_name)s(ExtMachInst machInst,
623 uint32_t _dest, uint32_t _op1, uint32_t _base);
624
625 %(BasicExecDeclare)s
626
627 %(InitiateAccDeclare)s
628
629 %(CompleteAccDeclare)s
630 };
631}};
632
633def template LoadStoreDImmDeclare {{
634 /**
635 * Static instruction class for "%(mnemonic)s".
636 */
637 class %(class_name)s : public %(base_class)s
638 {
639 public:
640
641 /// Constructor.
642 %(class_name)s(ExtMachInst machInst,
643 uint32_t _dest, uint32_t _dest2,
644 uint32_t _base, bool _add, int32_t _imm);
645
646 %(BasicExecDeclare)s
647
648 %(InitiateAccDeclare)s
649
650 %(CompleteAccDeclare)s
651 };
652}};
653
654def template StoreExDImmDeclare {{
655 /**
656 * Static instruction class for "%(mnemonic)s".
657 */
658 class %(class_name)s : public %(base_class)s
659 {
660 public:
661
662 /// Constructor.
663 %(class_name)s(ExtMachInst machInst,
664 uint32_t _result, uint32_t _dest, uint32_t _dest2,
665 uint32_t _base, bool _add, int32_t _imm);
666
667 %(BasicExecDeclare)s
668
669 %(InitiateAccDeclare)s
670
671 %(CompleteAccDeclare)s
672 };
673}};
674
675def template LoadStoreImmDeclare {{
676 /**
677 * Static instruction class for "%(mnemonic)s".
678 */
679 class %(class_name)s : public %(base_class)s
680 {
681 public:
682
683 /// Constructor.
684 %(class_name)s(ExtMachInst machInst,
685 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
686
687 %(BasicExecDeclare)s
688
689 %(InitiateAccDeclare)s
690
691 %(CompleteAccDeclare)s
692
693 virtual void
694 annotateFault(ArmFault *fault) {
695 %(fa_code)s
696 }
697 };
698}};
699
700def template StoreExImmDeclare {{

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705 {
706 public:
707
708 /// Constructor.
709 %(class_name)s(ExtMachInst machInst,
710 uint32_t _result, uint32_t _dest, uint32_t _base,
711 bool _add, int32_t _imm);
712
713 %(BasicExecDeclare)s
714
715 %(InitiateAccDeclare)s
716
717 %(CompleteAccDeclare)s
718 };
719}};
720
721def template StoreDRegDeclare {{
722 /**
723 * Static instruction class for "%(mnemonic)s".
724 */
725 class %(class_name)s : public %(base_class)s
726 {
727 public:
728
729 /// Constructor.
730 %(class_name)s(ExtMachInst machInst,
731 uint32_t _dest, uint32_t _dest2,
732 uint32_t _base, bool _add,
733 int32_t _shiftAmt, uint32_t _shiftType,
734 uint32_t _index);
735
736 %(BasicExecDeclare)s
737
738 %(InitiateAccDeclare)s
739
740 %(CompleteAccDeclare)s
741 };
742}};
743
744def template StoreRegDeclare {{
745 /**
746 * Static instruction class for "%(mnemonic)s".
747 */
748 class %(class_name)s : public %(base_class)s
749 {
750 public:
751
752 /// Constructor.
753 %(class_name)s(ExtMachInst machInst,
754 uint32_t _dest, uint32_t _base, bool _add,
755 int32_t _shiftAmt, uint32_t _shiftType,
756 uint32_t _index);
757
758 %(BasicExecDeclare)s
759
760 %(InitiateAccDeclare)s
761
762 %(CompleteAccDeclare)s
763
764 virtual void
765 annotateFault(ArmFault *fault) {
766 %(fa_code)s
767 }
768 };
769}};
770
771def template LoadDRegDeclare {{

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778
779 /// Constructor.
780 %(class_name)s(ExtMachInst machInst,
781 uint32_t _dest, uint32_t _dest2,
782 uint32_t _base, bool _add,
783 int32_t _shiftAmt, uint32_t _shiftType,
784 uint32_t _index);
785
786 %(BasicExecDeclare)s
787
788 %(InitiateAccDeclare)s
789
790 %(CompleteAccDeclare)s
791 };
792}};
793
794def template LoadRegDeclare {{
795 /**
796 * Static instruction class for "%(mnemonic)s".
797 */
798 class %(class_name)s : public %(base_class)s
799 {
800 public:
801
802 /// Constructor.
803 %(class_name)s(ExtMachInst machInst,
804 uint32_t _dest, uint32_t _base, bool _add,
805 int32_t _shiftAmt, uint32_t _shiftType,
806 uint32_t _index);
807
808 %(BasicExecDeclare)s
809
810 %(InitiateAccDeclare)s
811
812 %(CompleteAccDeclare)s
813
814 virtual void
815 annotateFault(ArmFault *fault) {
816 %(fa_code)s
817 }
818 };
819}};
820
821def template LoadImmDeclare {{
822 /**
823 * Static instruction class for "%(mnemonic)s".
824 */
825 class %(class_name)s : public %(base_class)s
826 {
827 public:
828
829 /// Constructor.
830 %(class_name)s(ExtMachInst machInst,
831 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
832
833 %(BasicExecDeclare)s
834
835 %(InitiateAccDeclare)s
836
837 %(CompleteAccDeclare)s
838
839 virtual void
840 annotateFault(ArmFault *fault) {
841 %(fa_code)s
842 }
843 };
844}};
845
846def template InitiateAccDeclare {{
847 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
848}};
849
850def template CompleteAccDeclare {{
851 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
852}};
853
854def template RfeConstructor {{
855 %(class_name)s::%(class_name)s(ExtMachInst machInst,
856 uint32_t _base, int _mode, bool _wb)
857 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
858 (IntRegIndex)_base, (AddrMode)_mode, _wb)
859 {
860 %(constructor)s;
861 if (!(condCode == COND_AL || condCode == COND_UC)) {

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