1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42
43
44def template SwapExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
47 {
48 Addr EA;
49 Fault fault = NoFault;
50
51 %(op_decl)s;
52 uint64_t memData = 0;
53 %(op_rd)s;
54 %(ea_code)s;
55
56 if (%(predicate_test)s)
57 {
58 %(preacc_code)s;
59
60 if (fault == NoFault) {
61 fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
62 EA, memAccessFlags, &memData);
63 }
64
65 if (fault == NoFault) {
66 %(postacc_code)s;
67 }
68
69 if (fault == NoFault) {
70 %(op_wb)s;
71 }
72 } else {
73 xc->setPredicate(false);
74 }
75
76 if (fault == NoFault && machInst.itstateMask != 0) {
77 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
78 }
79
80 return fault;
81 }
82}};
83
84def template SwapInitiateAcc {{
85 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
86 Trace::InstRecord *traceData) const
87 {
88 Addr EA;
89 Fault fault = NoFault;
90
91 %(op_decl)s;
92 uint64_t memData = 0;
93 %(op_rd)s;
94 %(ea_code)s;
95
96 if (%(predicate_test)s)
97 {
98 %(preacc_code)s;
99
100 if (fault == NoFault) {
101 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
102 memAccessFlags, &memData);
103 }
104
105 if (fault == NoFault) {
106 %(op_wb)s;
107 }
108 } else {
109 xc->setPredicate(false);
110 }
111
112 if (fault == NoFault && machInst.itstateMask != 0) {
113 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
114 }
115
116 return fault;
117 }
118}};
119
120def template SwapCompleteAcc {{
121 Fault %(class_name)s::completeAcc(PacketPtr pkt,
122 %(CPU_exec_context)s *xc,
123 Trace::InstRecord *traceData) const
124 {
125 Fault fault = NoFault;
126
127 %(op_decl)s;
128 %(op_rd)s;
129
130 if (%(predicate_test)s)
131 {
132 // ARM instructions will not have a pkt if the predicate is false
133 uint64_t memData = pkt->get<typeof(Mem)>();
134
135 %(postacc_code)s;
136
137 if (fault == NoFault) {
138 %(op_wb)s;
139 }
140 }
141
142 if (fault == NoFault && machInst.itstateMask != 0) {
143 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
144 }
145
146 return fault;
147 }
148}};
149
150def template LoadExecute {{
151 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
152 Trace::InstRecord *traceData) const
153 {
154 Addr EA;
155 Fault fault = NoFault;
156
157 %(op_decl)s;
158 %(op_rd)s;
159 %(ea_code)s;
160
161 if (%(predicate_test)s)
162 {
163 if (fault == NoFault) {
164 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
165 %(memacc_code)s;
166 }
167
168 if (fault == NoFault) {
169 %(op_wb)s;
170 }
171 } else {
172 xc->setPredicate(false);
173 }
174
175 if (fault == NoFault && machInst.itstateMask != 0) {
176 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
177 }
178
179 return fault;
180 }
181}};
182
183def template NeonLoadExecute {{
184 template <class Element>
185 Fault %(class_name)s<Element>::execute(
186 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
187 {
188 Addr EA;
189 Fault fault = NoFault;
190
191 %(op_decl)s;
192 %(mem_decl)s;
193 %(op_rd)s;
194 %(ea_code)s;
195
196 MemUnion memUnion;
197 uint8_t *dataPtr = memUnion.bytes;
198
199 if (%(predicate_test)s)
200 {
201 if (fault == NoFault) {
202 fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
203 %(memacc_code)s;
204 }
205
206 if (fault == NoFault) {
207 %(op_wb)s;
208 }
209 }
210
211 if (fault == NoFault && machInst.itstateMask != 0) {
212 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
213 }
214
215 return fault;
216 }
217}};
218
219def template StoreExecute {{
220 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
221 Trace::InstRecord *traceData) const
222 {
223 Addr EA;
224 Fault fault = NoFault;
225
226 %(op_decl)s;
227 %(op_rd)s;
228 %(ea_code)s;
229
230 if (%(predicate_test)s)
231 {
232 if (fault == NoFault) {
233 %(memacc_code)s;
234 }
235
236 if (fault == NoFault) {
237 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
238 memAccessFlags, NULL);
239 }
240
241 if (fault == NoFault) {
242 %(op_wb)s;
243 }
244 } else {
245 xc->setPredicate(false);
246 }
247
248 if (fault == NoFault && machInst.itstateMask != 0) {
249 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
250 }
251
252 return fault;
253 }
254}};
255
256def template NeonStoreExecute {{
257 template <class Element>
258 Fault %(class_name)s<Element>::execute(
259 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
260 {
261 Addr EA;
262 Fault fault = NoFault;
263
264 %(op_decl)s;
265 %(mem_decl)s;
266 %(op_rd)s;
267 %(ea_code)s;
268
269 MemUnion memUnion;
270 uint8_t *dataPtr = memUnion.bytes;
271
272 if (%(predicate_test)s)
273 {
274 if (fault == NoFault) {
275 %(memacc_code)s;
276 }
277
278 if (fault == NoFault) {
279 fault = xc->writeBytes(dataPtr, %(size)d, EA,
280 memAccessFlags, NULL);
281 }
282
283 if (fault == NoFault) {
284 %(op_wb)s;
285 }
286 }
287
288 if (fault == NoFault && machInst.itstateMask != 0) {
289 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
290 }
291
292 return fault;
293 }
294}};
295
296def template StoreExExecute {{
297 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
298 Trace::InstRecord *traceData) const
299 {
300 Addr EA;
301 Fault fault = NoFault;
302
303 %(op_decl)s;
304 %(op_rd)s;
305 %(ea_code)s;
306
307 if (%(predicate_test)s)
308 {
309 if (fault == NoFault) {
310 %(memacc_code)s;
311 }
312
313 uint64_t writeResult;
314
315 if (fault == NoFault) {
316 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
317 memAccessFlags, &writeResult);
318 }
319
320 if (fault == NoFault) {
321 %(postacc_code)s;
322 }
323
324 if (fault == NoFault) {
325 %(op_wb)s;
326 }
327 } else {
328 xc->setPredicate(false);
329 }
330
331 if (fault == NoFault && machInst.itstateMask != 0) {
332 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
333 }
334
335 return fault;
336 }
337}};
338
339def template StoreExInitiateAcc {{
340 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
341 Trace::InstRecord *traceData) const
342 {
343 Addr EA;
344 Fault fault = NoFault;
345
346 %(op_decl)s;
347 %(op_rd)s;
348 %(ea_code)s;
349
350 if (%(predicate_test)s)
351 {
352 if (fault == NoFault) {
353 %(memacc_code)s;
354 }
355
356 if (fault == NoFault) {
357 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
358 memAccessFlags, NULL);
359 }
360
361 // Need to write back any potential address register update
362 if (fault == NoFault) {
363 %(op_wb)s;
364 }
365 } else {
366 xc->setPredicate(false);
367 }
368
369 if (fault == NoFault && machInst.itstateMask != 0) {
370 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
371 }
372
373 return fault;
374 }
375}};
376
377def template StoreInitiateAcc {{
378 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
379 Trace::InstRecord *traceData) const
380 {
381 Addr EA;
382 Fault fault = NoFault;
383
384 %(op_decl)s;
385 %(op_rd)s;
386 %(ea_code)s;
387
388 if (%(predicate_test)s)
389 {
390 if (fault == NoFault) {
391 %(memacc_code)s;
392 }
393
394 if (fault == NoFault) {
395 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
396 memAccessFlags, NULL);
397 }
398
399 // Need to write back any potential address register update
400 if (fault == NoFault) {
401 %(op_wb)s;
402 }
403 } else {
404 xc->setPredicate(false);
405 }
406
407 if (fault == NoFault && machInst.itstateMask != 0) {
408 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
409 }
410
411 return fault;
412 }
413}};
414
415def template NeonStoreInitiateAcc {{
416 template <class Element>
417 Fault %(class_name)s<Element>::initiateAcc(
418 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
419 {
420 Addr EA;
421 Fault fault = NoFault;
422
423 %(op_decl)s;
424 %(mem_decl)s;
425 %(op_rd)s;
426 %(ea_code)s;
427
428 if (%(predicate_test)s)
429 {
430 MemUnion memUnion;
431 if (fault == NoFault) {
432 %(memacc_code)s;
433 }
434
435 if (fault == NoFault) {
436 fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
437 memAccessFlags, NULL);
438 }
439
440 // Need to write back any potential address register update
441 if (fault == NoFault) {
442 %(op_wb)s;
443 }
444 }
445
446 if (fault == NoFault && machInst.itstateMask != 0) {
447 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
448 }
449
450 return fault;
451 }
452}};
453
454def template LoadInitiateAcc {{
455 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
456 Trace::InstRecord *traceData) const
457 {
458 Addr EA;
459 Fault fault = NoFault;
460
461 %(op_src_decl)s;
462 %(op_rd)s;
463 %(ea_code)s;
464
465 if (%(predicate_test)s)
466 {
467 if (fault == NoFault) {
468 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
469 }
470 } else {
471 xc->setPredicate(false);
472 if (fault == NoFault && machInst.itstateMask != 0) {
473 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
474 }
475 }
476
477 return fault;
478 }
479}};
480
481def template NeonLoadInitiateAcc {{
482 template <class Element>
483 Fault %(class_name)s<Element>::initiateAcc(
484 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
485 {
486 Addr EA;
487 Fault fault = NoFault;
488
489 %(op_src_decl)s;
490 %(op_rd)s;
491 %(ea_code)s;
492
493 if (%(predicate_test)s)
494 {
495 if (fault == NoFault) {
496 fault = xc->readBytes(EA, NULL, %(size)d, memAccessFlags);
497 }
498 } else if (fault == NoFault && machInst.itstateMask != 0) {
499 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
500 }
501
502 return fault;
503 }
504}};
505
506def template LoadCompleteAcc {{
507 Fault %(class_name)s::completeAcc(PacketPtr pkt,
508 %(CPU_exec_context)s *xc,
509 Trace::InstRecord *traceData) const
510 {
511 Fault fault = NoFault;
512
513 %(op_decl)s;
514 %(op_rd)s;
515
516 if (%(predicate_test)s)
517 {
518 // ARM instructions will not have a pkt if the predicate is false
519 Mem = pkt->get<typeof(Mem)>();
520
521 if (fault == NoFault) {
522 %(memacc_code)s;
523 }
524
525 if (fault == NoFault) {
526 %(op_wb)s;
527 }
528 }
529
530 if (fault == NoFault && machInst.itstateMask != 0) {
531 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
532 }
533
534 return fault;
535 }
536}};
537
538def template NeonLoadCompleteAcc {{
539 template <class Element>
540 Fault %(class_name)s<Element>::completeAcc(
541 PacketPtr pkt, %(CPU_exec_context)s *xc,
542 Trace::InstRecord *traceData) const
543 {
544 Fault fault = NoFault;
545
546 %(mem_decl)s;
547 %(op_decl)s;
548 %(op_rd)s;
549
550 if (%(predicate_test)s)
551 {
552 // ARM instructions will not have a pkt if the predicate is false
553 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
554
555 if (fault == NoFault) {
556 %(memacc_code)s;
557 }
558
559 if (fault == NoFault) {
560 %(op_wb)s;
561 }
562 }
563
564 if (fault == NoFault && machInst.itstateMask != 0) {
565 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
566 }
567
568 return fault;
569 }
570}};
571
572def template StoreCompleteAcc {{
573 Fault %(class_name)s::completeAcc(PacketPtr pkt,
574 %(CPU_exec_context)s *xc,
575 Trace::InstRecord *traceData) const
576 {
577 Fault fault = NoFault;
578
579 %(op_decl)s;
580 %(op_rd)s;
581
582 if (%(predicate_test)s)
583 {
584 if (fault == NoFault) {
585 %(op_wb)s;
586 }
587 }
588
589 if (fault == NoFault && machInst.itstateMask != 0) {
590 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
591 }
592
593 return fault;
594 }
595}};
596
597def template NeonStoreCompleteAcc {{
598 template <class Element>
599 Fault %(class_name)s<Element>::completeAcc(
600 PacketPtr pkt, %(CPU_exec_context)s *xc,
601 Trace::InstRecord *traceData) const
602 {
603 Fault fault = NoFault;
604
605 %(op_decl)s;
606 %(op_rd)s;
607
608 if (%(predicate_test)s)
609 {
610 if (fault == NoFault) {
611 %(op_wb)s;
612 }
613 }
614
615 if (fault == NoFault && machInst.itstateMask != 0) {
616 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
617 }
618
619 return fault;
620 }
621}};
622
623def template StoreExCompleteAcc {{
624 Fault %(class_name)s::completeAcc(PacketPtr pkt,
625 %(CPU_exec_context)s *xc,
626 Trace::InstRecord *traceData) const
627 {
628 Fault fault = NoFault;
629
630 %(op_decl)s;
631 %(op_rd)s;
632
633 if (%(predicate_test)s)
634 {
635 uint64_t writeResult = pkt->req->getExtraData();
636 %(postacc_code)s;
637
638 if (fault == NoFault) {
639 %(op_wb)s;
640 }
641 }
642
643 if (fault == NoFault && machInst.itstateMask != 0) {
644 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
645 }
646
647 return fault;
648 }
649}};
650
651def template RfeDeclare {{
652 /**
653 * Static instruction class for "%(mnemonic)s".
654 */
655 class %(class_name)s : public %(base_class)s
656 {
657 public:
658
659 /// Constructor.
660 %(class_name)s(ExtMachInst machInst,
661 uint32_t _base, int _mode, bool _wb);
662
663 %(BasicExecDeclare)s
664
665 %(InitiateAccDeclare)s
666
667 %(CompleteAccDeclare)s
668 };
669}};
670
671def template SrsDeclare {{
672 /**
673 * Static instruction class for "%(mnemonic)s".
674 */
675 class %(class_name)s : public %(base_class)s
676 {
677 public:
678
679 /// Constructor.
680 %(class_name)s(ExtMachInst machInst,
681 uint32_t _regMode, int _mode, bool _wb);
682
683 %(BasicExecDeclare)s
684
685 %(InitiateAccDeclare)s
686
687 %(CompleteAccDeclare)s
688 };
689}};
690
691def template SwapDeclare {{
692 /**
693 * Static instruction class for "%(mnemonic)s".
694 */
695 class %(class_name)s : public %(base_class)s
696 {
697 public:
698
699 /// Constructor.
700 %(class_name)s(ExtMachInst machInst,
701 uint32_t _dest, uint32_t _op1, uint32_t _base);
702
703 %(BasicExecDeclare)s
704
705 %(InitiateAccDeclare)s
706
707 %(CompleteAccDeclare)s
708 };
709}};
710
711def template LoadStoreDImmDeclare {{
712 /**
713 * Static instruction class for "%(mnemonic)s".
714 */
715 class %(class_name)s : public %(base_class)s
716 {
717 public:
718
719 /// Constructor.
720 %(class_name)s(ExtMachInst machInst,
721 uint32_t _dest, uint32_t _dest2,
722 uint32_t _base, bool _add, int32_t _imm);
723
724 %(BasicExecDeclare)s
725
726 %(InitiateAccDeclare)s
727
728 %(CompleteAccDeclare)s
729 };
730}};
731
732def template StoreExDImmDeclare {{
733 /**
734 * Static instruction class for "%(mnemonic)s".
735 */
736 class %(class_name)s : public %(base_class)s
737 {
738 public:
739
740 /// Constructor.
741 %(class_name)s(ExtMachInst machInst,
742 uint32_t _result, uint32_t _dest, uint32_t _dest2,
743 uint32_t _base, bool _add, int32_t _imm);
744
745 %(BasicExecDeclare)s
746
747 %(InitiateAccDeclare)s
748
749 %(CompleteAccDeclare)s
750 };
751}};
752
753def template LoadStoreImmDeclare {{
754 /**
755 * Static instruction class for "%(mnemonic)s".
756 */
757 class %(class_name)s : public %(base_class)s
758 {
759 public:
760
761 /// Constructor.
762 %(class_name)s(ExtMachInst machInst,
763 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
764
765 %(BasicExecDeclare)s
766
767 %(InitiateAccDeclare)s
768
769 %(CompleteAccDeclare)s
770 };
771}};
772
773def template StoreExImmDeclare {{
774 /**
775 * Static instruction class for "%(mnemonic)s".
776 */
777 class %(class_name)s : public %(base_class)s
778 {
779 public:
780
781 /// Constructor.
782 %(class_name)s(ExtMachInst machInst,
783 uint32_t _result, uint32_t _dest, uint32_t _base,
784 bool _add, int32_t _imm);
785
786 %(BasicExecDeclare)s
787
788 %(InitiateAccDeclare)s
789
790 %(CompleteAccDeclare)s
791 };
792}};
793
794def template LoadStoreDRegDeclare {{
795 /**
796 * Static instruction class for "%(mnemonic)s".
797 */
798 class %(class_name)s : public %(base_class)s
799 {
800 public:
801
802 /// Constructor.
803 %(class_name)s(ExtMachInst machInst,
804 uint32_t _dest, uint32_t _dest2,
805 uint32_t _base, bool _add,
806 int32_t _shiftAmt, uint32_t _shiftType,
807 uint32_t _index);
808
809 %(BasicExecDeclare)s
810
811 %(InitiateAccDeclare)s
812
813 %(CompleteAccDeclare)s
814 };
815}};
816
817def template LoadStoreRegDeclare {{
818 /**
819 * Static instruction class for "%(mnemonic)s".
820 */
821 class %(class_name)s : public %(base_class)s
822 {
823 public:
824
825 /// Constructor.
826 %(class_name)s(ExtMachInst machInst,
827 uint32_t _dest, uint32_t _base, bool _add,
828 int32_t _shiftAmt, uint32_t _shiftType,
829 uint32_t _index);
830
831 %(BasicExecDeclare)s
832
833 %(InitiateAccDeclare)s
834
835 %(CompleteAccDeclare)s
836 };
837}};
838
839def template InitiateAccDeclare {{
840 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
841}};
842
843def template CompleteAccDeclare {{
844 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
845}};
846
847def template RfeConstructor {{
848 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
849 uint32_t _base, int _mode, bool _wb)
850 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
851 (IntRegIndex)_base, (AddrMode)_mode, _wb)
852 {
853 %(constructor)s;
854 }
855}};
856
857def template SrsConstructor {{
858 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
859 uint32_t _regMode, int _mode, bool _wb)
860 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
861 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
862 {
863 %(constructor)s;
864 }
865}};
866
867def template SwapConstructor {{
868 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
869 uint32_t _dest, uint32_t _op1, uint32_t _base)
870 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
871 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
872 {
873 %(constructor)s;
874 }
875}};
876
877def template LoadStoreDImmConstructor {{
878 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
879 uint32_t _dest, uint32_t _dest2,
880 uint32_t _base, bool _add, int32_t _imm)
881 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
882 (IntRegIndex)_dest, (IntRegIndex)_dest2,
883 (IntRegIndex)_base, _add, _imm)
884 {
885 %(constructor)s;
886 }
887}};
888
889def template StoreExDImmConstructor {{
890 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
891 uint32_t _result, uint32_t _dest, uint32_t _dest2,
892 uint32_t _base, bool _add, int32_t _imm)
893 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
894 (IntRegIndex)_result,
895 (IntRegIndex)_dest, (IntRegIndex)_dest2,
896 (IntRegIndex)_base, _add, _imm)
897 {
898 %(constructor)s;
899 }
900}};
901
902def template LoadStoreImmConstructor {{
903 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
904 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
905 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
906 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
907 {
908 %(constructor)s;
909 }
910}};
911
912def template StoreExImmConstructor {{
913 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
914 uint32_t _result, uint32_t _dest, uint32_t _base,
915 bool _add, int32_t _imm)
916 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
917 (IntRegIndex)_result, (IntRegIndex)_dest,
918 (IntRegIndex)_base, _add, _imm)
919 {
920 %(constructor)s;
921 }
922}};
923
924def template LoadStoreDRegConstructor {{
925 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
926 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
927 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
928 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
929 (IntRegIndex)_dest, (IntRegIndex)_dest2,
930 (IntRegIndex)_base, _add,
931 _shiftAmt, (ArmShiftType)_shiftType,
932 (IntRegIndex)_index)
933 {
934 %(constructor)s;
935 }
936}};
937
938def template LoadStoreRegConstructor {{
939 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
940 uint32_t _dest, uint32_t _base, bool _add,
941 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
942 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
943 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
944 _shiftAmt, (ArmShiftType)_shiftType,
945 (IntRegIndex)_index)
946 {
947 %(constructor)s;
948 }
949}};