macromem.isa (7646:a444dbee8c07) | macromem.isa (7848:cc5e64f8423f) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 55 unchanged lines hidden (view full) --- 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; |
72 if (!(condCode == COND_AL || condCode == COND_UC)) { 73 for (int x = 0; x < _numDestRegs; x++) { 74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 75 } 76 } |
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72 } 73}}; 74 75//////////////////////////////////////////////////////////////////// 76// 77// Neon load/store microops 78// 79 --- 4 unchanged lines hidden (view full) --- 84 public: 85 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 86 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 87 : %(base_class)s("%(mnemonic)s", machInst, 88 %(op_class)s, _dest, _ura, _imm) 89 { 90 memAccessFlags |= extraMemFlags; 91 %(constructor)s; | 77 } 78}}; 79 80//////////////////////////////////////////////////////////////////// 81// 82// Neon load/store microops 83// 84 --- 4 unchanged lines hidden (view full) --- 89 public: 90 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 92 : %(base_class)s("%(mnemonic)s", machInst, 93 %(op_class)s, _dest, _ura, _imm) 94 { 95 memAccessFlags |= extraMemFlags; 96 %(constructor)s; |
97 if (!(condCode == COND_AL || condCode == COND_UC)) { 98 for (int x = 0; x < _numDestRegs; x++) { 99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 100 } 101 } |
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92 } 93 94 %(BasicExecDeclare)s 95 %(InitiateAccDeclare)s 96 %(CompleteAccDeclare)s 97 }; 98}}; 99 --- 16 unchanged lines hidden (view full) --- 116 %(class_name)s::%(class_name)s(ExtMachInst machInst, 117 RegIndex _ura, 118 RegIndex _urb, 119 RegIndex _urc) 120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 121 _ura, _urb, _urc) 122 { 123 %(constructor)s; | 102 } 103 104 %(BasicExecDeclare)s 105 %(InitiateAccDeclare)s 106 %(CompleteAccDeclare)s 107 }; 108}}; 109 --- 16 unchanged lines hidden (view full) --- 126 %(class_name)s::%(class_name)s(ExtMachInst machInst, 127 RegIndex _ura, 128 RegIndex _urb, 129 RegIndex _urc) 130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 131 _ura, _urb, _urc) 132 { 133 %(constructor)s; |
134 if (!(condCode == COND_AL || condCode == COND_UC)) { 135 for (int x = 0; x < _numDestRegs; x++) { 136 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 137 } 138 } |
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124 } 125}}; 126 127def template MicroNeonMemExecDeclare {{ 128 template 129 Fault %(class_name)s<%(targs)s>::execute( 130 %(CPU_exec_context)s *, Trace::InstRecord *) const; 131 template --- 21 unchanged lines hidden (view full) --- 153 { 154 public: 155 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 156 uint8_t _step) : 157 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 158 _dest, _op1, _step) 159 { 160 %(constructor)s; | 139 } 140}}; 141 142def template MicroNeonMemExecDeclare {{ 143 template 144 Fault %(class_name)s<%(targs)s>::execute( 145 %(CPU_exec_context)s *, Trace::InstRecord *) const; 146 template --- 21 unchanged lines hidden (view full) --- 168 { 169 public: 170 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 171 uint8_t _step) : 172 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 173 _dest, _op1, _step) 174 { 175 %(constructor)s; |
176 if (!(condCode == COND_AL || condCode == COND_UC)) { 177 for (int x = 0; x < _numDestRegs; x++) { 178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 179 } 180 } |
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161 } 162 163 %(BasicExecDeclare)s 164 }; 165}}; 166 167def template MicroNeonMixExecute {{ 168 template <class Element> --- 34 unchanged lines hidden (view full) --- 203 { 204 public: 205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 206 uint8_t _step, unsigned _lane) : 207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 208 _dest, _op1, _step, _lane) 209 { 210 %(constructor)s; | 181 } 182 183 %(BasicExecDeclare)s 184 }; 185}}; 186 187def template MicroNeonMixExecute {{ 188 template <class Element> --- 34 unchanged lines hidden (view full) --- 223 { 224 public: 225 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 226 uint8_t _step, unsigned _lane) : 227 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 228 _dest, _op1, _step, _lane) 229 { 230 %(constructor)s; |
231 if (!(condCode == COND_AL || condCode == COND_UC)) { 232 for (int x = 0; x < _numDestRegs; x++) { 233 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 234 } 235 } |
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211 } 212 213 %(BasicExecDeclare)s 214 }; 215}}; 216 217//////////////////////////////////////////////////////////////////// 218// --- 12 unchanged lines hidden (view full) --- 231def template MicroIntMovConstructor {{ 232 %(class_name)s::%(class_name)s(ExtMachInst machInst, 233 RegIndex _ura, 234 RegIndex _urb) 235 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 236 _ura, _urb) 237 { 238 %(constructor)s; | 236 } 237 238 %(BasicExecDeclare)s 239 }; 240}}; 241 242//////////////////////////////////////////////////////////////////// 243// --- 12 unchanged lines hidden (view full) --- 256def template MicroIntMovConstructor {{ 257 %(class_name)s::%(class_name)s(ExtMachInst machInst, 258 RegIndex _ura, 259 RegIndex _urb) 260 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 261 _ura, _urb) 262 { 263 %(constructor)s; |
264 if (!(condCode == COND_AL || condCode == COND_UC)) { 265 for (int x = 0; x < _numDestRegs; x++) { 266 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 267 } 268 } |
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239 } 240}}; 241 242//////////////////////////////////////////////////////////////////// 243// 244// Integer = Integer op Immediate microops 245// 246 --- 12 unchanged lines hidden (view full) --- 259 %(class_name)s::%(class_name)s(ExtMachInst machInst, 260 RegIndex _ura, 261 RegIndex _urb, 262 int32_t _imm) 263 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 264 _ura, _urb, _imm) 265 { 266 %(constructor)s; | 269 } 270}}; 271 272//////////////////////////////////////////////////////////////////// 273// 274// Integer = Integer op Immediate microops 275// 276 --- 12 unchanged lines hidden (view full) --- 289 %(class_name)s::%(class_name)s(ExtMachInst machInst, 290 RegIndex _ura, 291 RegIndex _urb, 292 int32_t _imm) 293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 294 _ura, _urb, _imm) 295 { 296 %(constructor)s; |
297 if (!(condCode == COND_AL || condCode == COND_UC)) { 298 for (int x = 0; x < _numDestRegs; x++) { 299 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 300 } 301 } |
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267 } 268}}; 269 270def template MicroIntRegDeclare {{ 271 class %(class_name)s : public %(base_class)s 272 { 273 public: 274 %(class_name)s(ExtMachInst machInst, --- 6 unchanged lines hidden (view full) --- 281def template MicroIntRegConstructor {{ 282 %(class_name)s::%(class_name)s(ExtMachInst machInst, 283 RegIndex _ura, RegIndex _urb, RegIndex _urc, 284 int32_t _shiftAmt, ArmShiftType _shiftType) 285 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 286 _ura, _urb, _urc, _shiftAmt, _shiftType) 287 { 288 %(constructor)s; | 302 } 303}}; 304 305def template MicroIntRegDeclare {{ 306 class %(class_name)s : public %(base_class)s 307 { 308 public: 309 %(class_name)s(ExtMachInst machInst, --- 6 unchanged lines hidden (view full) --- 316def template MicroIntRegConstructor {{ 317 %(class_name)s::%(class_name)s(ExtMachInst machInst, 318 RegIndex _ura, RegIndex _urb, RegIndex _urc, 319 int32_t _shiftAmt, ArmShiftType _shiftType) 320 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 321 _ura, _urb, _urc, _shiftAmt, _shiftType) 322 { 323 %(constructor)s; |
324 if (!(condCode == COND_AL || condCode == COND_UC)) { 325 for (int x = 0; x < _numDestRegs; x++) { 326 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 327 } 328 } |
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289 } 290}}; 291 292//////////////////////////////////////////////////////////////////// 293// 294// Macro Memory-format instructions 295// 296 --- 15 unchanged lines hidden (view full) --- 312def template MacroMemConstructor {{ 313%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 314 bool index, bool up, bool user, bool writeback, bool load, 315 uint32_t reglist) 316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 317 index, up, user, writeback, load, reglist) 318{ 319 %(constructor)s; | 329 } 330}}; 331 332//////////////////////////////////////////////////////////////////// 333// 334// Macro Memory-format instructions 335// 336 --- 15 unchanged lines hidden (view full) --- 352def template MacroMemConstructor {{ 353%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 354 bool index, bool up, bool user, bool writeback, bool load, 355 uint32_t reglist) 356 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 357 index, up, user, writeback, load, reglist) 358{ 359 %(constructor)s; |
360 if (!(condCode == COND_AL || condCode == COND_UC)) { 361 for (int x = 0; x < _numDestRegs; x++) { 362 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 363 } 364 } |
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320} 321 322}}; 323 324def template VMemMultDeclare {{ 325class %(class_name)s : public %(base_class)s 326{ 327 public: --- 8 unchanged lines hidden (view full) --- 336def template VMemMultConstructor {{ 337%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 338 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 339 uint32_t size, uint32_t align, RegIndex rm) 340 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 341 rn, vd, regs, inc, size, align, rm) 342{ 343 %(constructor)s; | 365} 366 367}}; 368 369def template VMemMultDeclare {{ 370class %(class_name)s : public %(base_class)s 371{ 372 public: --- 8 unchanged lines hidden (view full) --- 381def template VMemMultConstructor {{ 382%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 383 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 384 uint32_t size, uint32_t align, RegIndex rm) 385 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 386 rn, vd, regs, inc, size, align, rm) 387{ 388 %(constructor)s; |
389 if (!(condCode == COND_AL || condCode == COND_UC)) { 390 for (int x = 0; x < _numDestRegs; x++) { 391 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 392 } 393 } |
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344} 345}}; 346 347def template VMemSingleDeclare {{ 348class %(class_name)s : public %(base_class)s 349{ 350 public: 351 // Constructor --- 7 unchanged lines hidden (view full) --- 359def template VMemSingleConstructor {{ 360%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 361 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 362 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 363 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 364 rn, vd, regs, inc, size, align, rm, lane) 365{ 366 %(constructor)s; | 394} 395}}; 396 397def template VMemSingleDeclare {{ 398class %(class_name)s : public %(base_class)s 399{ 400 public: 401 // Constructor --- 7 unchanged lines hidden (view full) --- 409def template VMemSingleConstructor {{ 410%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 411 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 412 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 413 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 414 rn, vd, regs, inc, size, align, rm, lane) 415{ 416 %(constructor)s; |
417 if (!(condCode == COND_AL || condCode == COND_UC)) { 418 for (int x = 0; x < _numDestRegs; x++) { 419 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 420 } 421 } |
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367} 368}}; 369 370def template MacroVFPMemDeclare {{ 371/** 372 * Static instructions class for a store multiple instruction 373 */ 374class %(class_name)s : public %(base_class)s --- 10 unchanged lines hidden (view full) --- 385def template MacroVFPMemConstructor {{ 386%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 387 RegIndex vd, bool single, bool up, bool writeback, bool load, 388 uint32_t offset) 389 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 390 vd, single, up, writeback, load, offset) 391{ 392 %(constructor)s; | 422} 423}}; 424 425def template MacroVFPMemDeclare {{ 426/** 427 * Static instructions class for a store multiple instruction 428 */ 429class %(class_name)s : public %(base_class)s --- 10 unchanged lines hidden (view full) --- 440def template MacroVFPMemConstructor {{ 441%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 442 RegIndex vd, bool single, bool up, bool writeback, bool load, 443 uint32_t offset) 444 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 445 vd, single, up, writeback, load, offset) 446{ 447 %(constructor)s; |
448 if (!(condCode == COND_AL || condCode == COND_UC)) { 449 for (int x = 0; x < _numDestRegs; x++) { 450 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 451 } 452 } |
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393} 394 395}}; | 453} 454 455}}; |