macromem.isa (7176:94f0a9ac9bbc) | macromem.isa (7639:8c09b7ff5b57) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 60 unchanged lines hidden (view full) --- 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 } 73}}; 74 75//////////////////////////////////////////////////////////////////// 76// | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 60 unchanged lines hidden (view full) --- 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 } 73}}; 74 75//////////////////////////////////////////////////////////////////// 76// |
77// Integer = Integer op Immediate microops | 77// Neon load/store microops |
78// 79 | 78// 79 |
80def template MicroNeonMemDeclare {{ 81 template <class Element> 82 class %(class_name)s : public %(base_class)s 83 { 84 public: 85 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 86 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 87 : %(base_class)s("%(mnemonic)s", machInst, 88 %(op_class)s, _dest, _ura, _imm) 89 { 90 memAccessFlags |= extraMemFlags; 91 %(constructor)s; 92 } 93 94 %(BasicExecDeclare)s 95 %(InitiateAccDeclare)s 96 %(CompleteAccDeclare)s 97 }; 98}}; 99 100//////////////////////////////////////////////////////////////////// 101// 102// Integer = Integer op Integer microops 103// 104 |
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80def template MicroIntDeclare {{ 81 class %(class_name)s : public %(base_class)s 82 { 83 public: 84 %(class_name)s(ExtMachInst machInst, | 105def template MicroIntDeclare {{ 106 class %(class_name)s : public %(base_class)s 107 { 108 public: 109 %(class_name)s(ExtMachInst machInst, |
110 RegIndex _ura, RegIndex _urb, RegIndex _urc); 111 %(BasicExecDeclare)s 112 }; 113}}; 114 115def template MicroIntConstructor {{ 116 %(class_name)s::%(class_name)s(ExtMachInst machInst, 117 RegIndex _ura, 118 RegIndex _urb, 119 RegIndex _urc) 120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 121 _ura, _urb, _urc) 122 { 123 %(constructor)s; 124 } 125}}; 126 127def template MicroNeonMemExecDeclare {{ 128 template 129 Fault %(class_name)s<%(targs)s>::execute( 130 %(CPU_exec_context)s *, Trace::InstRecord *) const; 131 template 132 Fault %(class_name)s<%(targs)s>::initiateAcc( 133 %(CPU_exec_context)s *, Trace::InstRecord *) const; 134 template 135 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 136 %(CPU_exec_context)s *, Trace::InstRecord *) const; 137}}; 138 139def template MicroNeonExecDeclare {{ 140 template 141 Fault %(class_name)s<%(targs)s>::execute( 142 %(CPU_exec_context)s *, Trace::InstRecord *) const; 143}}; 144 145//////////////////////////////////////////////////////////////////// 146// 147// Neon (de)interlacing microops 148// 149 150def template MicroNeonMixDeclare {{ 151 template <class Element> 152 class %(class_name)s : public %(base_class)s 153 { 154 public: 155 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 156 uint8_t _step) : 157 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 158 _dest, _op1, _step) 159 { 160 %(constructor)s; 161 } 162 163 %(BasicExecDeclare)s 164 }; 165}}; 166 167def template MicroNeonMixExecute {{ 168 template <class Element> 169 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 170 Trace::InstRecord *traceData) const 171 { 172 Fault fault = NoFault; 173 uint64_t resTemp = 0; 174 resTemp = resTemp; 175 %(op_decl)s; 176 %(op_rd)s; 177 178 if (%(predicate_test)s) 179 { 180 %(code)s; 181 if (fault == NoFault) 182 { 183 %(op_wb)s; 184 } 185 } 186 187 if (fault == NoFault && machInst.itstateMask != 0) { 188 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 189 } 190 191 return fault; 192 } 193}}; 194 195//////////////////////////////////////////////////////////////////// 196// 197// Neon (un)packing microops using a particular lane 198// 199 200def template MicroNeonMixLaneDeclare {{ 201 template <class Element> 202 class %(class_name)s : public %(base_class)s 203 { 204 public: 205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 206 uint8_t _step, unsigned _lane) : 207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 208 _dest, _op1, _step, _lane) 209 { 210 %(constructor)s; 211 } 212 213 %(BasicExecDeclare)s 214 }; 215}}; 216 217//////////////////////////////////////////////////////////////////// 218// 219// Integer = Integer op Immediate microops 220// 221 222def template MicroIntImmDeclare {{ 223 class %(class_name)s : public %(base_class)s 224 { 225 public: 226 %(class_name)s(ExtMachInst machInst, |
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85 RegIndex _ura, RegIndex _urb, 86 uint8_t _imm); 87 %(BasicExecDeclare)s 88 }; 89}}; 90 | 227 RegIndex _ura, RegIndex _urb, 228 uint8_t _imm); 229 %(BasicExecDeclare)s 230 }; 231}}; 232 |
91def template MicroIntConstructor {{ | 233def template MicroIntImmConstructor {{ |
92 %(class_name)s::%(class_name)s(ExtMachInst machInst, 93 RegIndex _ura, 94 RegIndex _urb, 95 uint8_t _imm) 96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 97 _ura, _urb, _imm) 98 { 99 %(constructor)s; --- 27 unchanged lines hidden (view full) --- 127 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 128 index, up, user, writeback, load, reglist) 129{ 130 %(constructor)s; 131} 132 133}}; 134 | 234 %(class_name)s::%(class_name)s(ExtMachInst machInst, 235 RegIndex _ura, 236 RegIndex _urb, 237 uint8_t _imm) 238 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 239 _ura, _urb, _imm) 240 { 241 %(constructor)s; --- 27 unchanged lines hidden (view full) --- 269 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 270 index, up, user, writeback, load, reglist) 271{ 272 %(constructor)s; 273} 274 275}}; 276 |
277def template VMemMultDeclare {{ 278class %(class_name)s : public %(base_class)s 279{ 280 public: 281 // Constructor 282 %(class_name)s(ExtMachInst machInst, unsigned width, 283 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 284 uint32_t size, uint32_t align, RegIndex rm); 285 %(BasicExecPanic)s 286}; 287}}; 288 289def template VMemMultConstructor {{ 290%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 291 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 292 uint32_t size, uint32_t align, RegIndex rm) 293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 294 rn, vd, regs, inc, size, align, rm) 295{ 296 %(constructor)s; 297} 298}}; 299 300def template VMemSingleDeclare {{ 301class %(class_name)s : public %(base_class)s 302{ 303 public: 304 // Constructor 305 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 306 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 307 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 308 %(BasicExecPanic)s 309}; 310}}; 311 312def template VMemSingleConstructor {{ 313%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 314 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 315 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 317 rn, vd, regs, inc, size, align, rm, lane) 318{ 319 %(constructor)s; 320} 321}}; 322 |
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135def template MacroVFPMemDeclare {{ 136/** 137 * Static instructions class for a store multiple instruction 138 */ 139class %(class_name)s : public %(base_class)s 140{ 141 public: 142 // Constructor --- 18 unchanged lines hidden --- | 323def template MacroVFPMemDeclare {{ 324/** 325 * Static instructions class for a store multiple instruction 326 */ 327class %(class_name)s : public %(base_class)s 328{ 329 public: 330 // Constructor --- 18 unchanged lines hidden --- |