1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42// Gabe Black 43 44//////////////////////////////////////////////////////////////////// 45// 46// Load/store microops 47// 48 49def template MicroMemDeclare {{ 50 class %(class_name)s : public %(base_class)s 51 { 52 public: 53 %(class_name)s(ExtMachInst machInst, 54 RegIndex _ura, RegIndex _urb, bool _up, 55 uint8_t _imm); 56 %(BasicExecDeclare)s 57 %(InitiateAccDeclare)s 58 %(CompleteAccDeclare)s 59 }; 60}}; 61 62def template MicroMemConstructor {{ 63 %(class_name)s::%(class_name)s(ExtMachInst machInst, 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 if (!(condCode == COND_AL || condCode == COND_UC)) { 73 for (int x = 0; x < _numDestRegs; x++) { 74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 75 } 76 } 77 } 78}}; 79 80//////////////////////////////////////////////////////////////////// 81// 82// Neon load/store microops 83// 84 85def template MicroNeonMemDeclare {{ 86 template <class Element> 87 class %(class_name)s : public %(base_class)s 88 { 89 public: 90 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 92 : %(base_class)s("%(mnemonic)s", machInst, 93 %(op_class)s, _dest, _ura, _imm) 94 { 95 memAccessFlags |= extraMemFlags; 96 %(constructor)s; 97 if (!(condCode == COND_AL || condCode == COND_UC)) { 98 for (int x = 0; x < _numDestRegs; x++) { 99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 100 } 101 } 102 } 103 104 %(BasicExecDeclare)s 105 %(InitiateAccDeclare)s 106 %(CompleteAccDeclare)s 107 }; 108}}; 109 110//////////////////////////////////////////////////////////////////// 111// 112// PC = Integer(ura) 113// CPSR = Integer(urb) 114// 115 116def template MicroSetPCCPSRDeclare {{ 117 class %(class_name)s : public %(base_class)s 118 { 119 public: 120 %(class_name)s(ExtMachInst machInst, 121 IntRegIndex _ura, 122 IntRegIndex _urb, 123 IntRegIndex _urc); 124 %(BasicExecDeclare)s 125 }; 126}}; 127 128def template MicroSetPCCPSRConstructor {{ 129 %(class_name)s::%(class_name)s(ExtMachInst machInst, 130 IntRegIndex _ura, 131 IntRegIndex _urb, 132 IntRegIndex _urc) 133 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 134 _ura, _urb, _urc) 135 { 136 %(constructor)s; 137 if (!(condCode == COND_AL || condCode == COND_UC)) { 138 for (int x = 0; x < _numDestRegs; x++) { 139 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 140 } 141 } 142 } 143}}; 144 145//////////////////////////////////////////////////////////////////// 146// 147// Integer = Integer op Integer microops 148// 149 150def template MicroIntDeclare {{ 151 class %(class_name)s : public %(base_class)s 152 { 153 public: 154 %(class_name)s(ExtMachInst machInst, 155 RegIndex _ura, RegIndex _urb, RegIndex _urc); 156 %(BasicExecDeclare)s 157 }; 158}}; 159 160def template MicroIntConstructor {{ 161 %(class_name)s::%(class_name)s(ExtMachInst machInst, 162 RegIndex _ura, 163 RegIndex _urb, 164 RegIndex _urc) 165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 166 _ura, _urb, _urc) 167 { 168 %(constructor)s; 169 if (!(condCode == COND_AL || condCode == COND_UC)) { 170 for (int x = 0; x < _numDestRegs; x++) { 171 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 172 } 173 } 174 } 175}}; 176 177def template MicroNeonMemExecDeclare {{ 178 template 179 Fault %(class_name)s<%(targs)s>::execute( 180 %(CPU_exec_context)s *, Trace::InstRecord *) const; 181 template 182 Fault %(class_name)s<%(targs)s>::initiateAcc( 183 %(CPU_exec_context)s *, Trace::InstRecord *) const; 184 template 185 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 186 %(CPU_exec_context)s *, Trace::InstRecord *) const; 187}}; 188 189def template MicroNeonExecDeclare {{ 190 template 191 Fault %(class_name)s<%(targs)s>::execute( 192 %(CPU_exec_context)s *, Trace::InstRecord *) const; 193}}; 194 195//////////////////////////////////////////////////////////////////// 196// 197// Neon (de)interlacing microops 198// 199 200def template MicroNeonMixDeclare {{ 201 template <class Element> 202 class %(class_name)s : public %(base_class)s 203 { 204 public: 205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 206 uint8_t _step) : 207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 208 _dest, _op1, _step) 209 { 210 %(constructor)s; 211 if (!(condCode == COND_AL || condCode == COND_UC)) { 212 for (int x = 0; x < _numDestRegs; x++) { 213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 214 } 215 } 216 } 217 218 %(BasicExecDeclare)s 219 }; 220}}; 221 222def template MicroNeonMixExecute {{ 223 template <class Element> 224 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 225 Trace::InstRecord *traceData) const 226 { 227 Fault fault = NoFault; 228 uint64_t resTemp = 0; 229 resTemp = resTemp; 230 %(op_decl)s; 231 %(op_rd)s; 232 233 if (%(predicate_test)s) 234 { 235 %(code)s; 236 if (fault == NoFault) 237 { 238 %(op_wb)s; 239 } 240 } else { 241 xc->setPredicate(false); 242 } 243 |
244 return fault; 245 } 246}}; 247 248//////////////////////////////////////////////////////////////////// 249// 250// Neon (un)packing microops using a particular lane 251// 252 253def template MicroNeonMixLaneDeclare {{ 254 template <class Element> 255 class %(class_name)s : public %(base_class)s 256 { 257 public: 258 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 259 uint8_t _step, unsigned _lane) : 260 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 261 _dest, _op1, _step, _lane) 262 { 263 %(constructor)s; 264 if (!(condCode == COND_AL || condCode == COND_UC)) { 265 for (int x = 0; x < _numDestRegs; x++) { 266 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 267 } 268 } 269 } 270 271 %(BasicExecDeclare)s 272 }; 273}}; 274 275//////////////////////////////////////////////////////////////////// 276// 277// Integer = Integer 278// 279 280def template MicroIntMovDeclare {{ 281 class %(class_name)s : public %(base_class)s 282 { 283 public: 284 %(class_name)s(ExtMachInst machInst, 285 RegIndex _ura, RegIndex _urb); 286 %(BasicExecDeclare)s 287 }; 288}}; 289def template MicroIntMovConstructor {{ 290 %(class_name)s::%(class_name)s(ExtMachInst machInst, 291 RegIndex _ura, 292 RegIndex _urb) 293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 294 _ura, _urb) 295 { 296 %(constructor)s; 297 if (!(condCode == COND_AL || condCode == COND_UC)) { 298 for (int x = 0; x < _numDestRegs; x++) { 299 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 300 } 301 } 302 } 303}}; 304 305//////////////////////////////////////////////////////////////////// 306// 307// Integer = Integer op Immediate microops 308// 309 310def template MicroIntImmDeclare {{ 311 class %(class_name)s : public %(base_class)s 312 { 313 public: 314 %(class_name)s(ExtMachInst machInst, 315 RegIndex _ura, RegIndex _urb, 316 int32_t _imm); 317 %(BasicExecDeclare)s 318 }; 319}}; 320 321def template MicroIntImmConstructor {{ 322 %(class_name)s::%(class_name)s(ExtMachInst machInst, 323 RegIndex _ura, 324 RegIndex _urb, 325 int32_t _imm) 326 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 327 _ura, _urb, _imm) 328 { 329 %(constructor)s; 330 if (!(condCode == COND_AL || condCode == COND_UC)) { 331 for (int x = 0; x < _numDestRegs; x++) { 332 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 333 } 334 } 335 } 336}}; 337 338def template MicroIntRegDeclare {{ 339 class %(class_name)s : public %(base_class)s 340 { 341 public: 342 %(class_name)s(ExtMachInst machInst, 343 RegIndex _ura, RegIndex _urb, RegIndex _urc, 344 int32_t _shiftAmt, ArmShiftType _shiftType); 345 %(BasicExecDeclare)s 346 }; 347}}; 348 349def template MicroIntRegConstructor {{ 350 %(class_name)s::%(class_name)s(ExtMachInst machInst, 351 RegIndex _ura, RegIndex _urb, RegIndex _urc, 352 int32_t _shiftAmt, ArmShiftType _shiftType) 353 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 354 _ura, _urb, _urc, _shiftAmt, _shiftType) 355 { 356 %(constructor)s; 357 if (!(condCode == COND_AL || condCode == COND_UC)) { 358 for (int x = 0; x < _numDestRegs; x++) { 359 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 360 } 361 } 362 } 363}}; 364 365//////////////////////////////////////////////////////////////////// 366// 367// Macro Memory-format instructions 368// 369 370def template MacroMemDeclare {{ 371/** 372 * Static instructions class for a store multiple instruction 373 */ 374class %(class_name)s : public %(base_class)s 375{ 376 public: 377 // Constructor 378 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 379 bool index, bool up, bool user, bool writeback, bool load, 380 uint32_t reglist); 381 %(BasicExecPanic)s 382}; 383}}; 384 385def template MacroMemConstructor {{ 386%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 387 bool index, bool up, bool user, bool writeback, bool load, 388 uint32_t reglist) 389 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 390 index, up, user, writeback, load, reglist) 391{ 392 %(constructor)s; 393 if (!(condCode == COND_AL || condCode == COND_UC)) { 394 for (int x = 0; x < _numDestRegs; x++) { 395 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 396 } 397 } 398} 399 400}}; 401 402def template VMemMultDeclare {{ 403class %(class_name)s : public %(base_class)s 404{ 405 public: 406 // Constructor 407 %(class_name)s(ExtMachInst machInst, unsigned width, 408 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 409 uint32_t size, uint32_t align, RegIndex rm); 410 %(BasicExecPanic)s 411}; 412}}; 413 414def template VMemMultConstructor {{ 415%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 416 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 417 uint32_t size, uint32_t align, RegIndex rm) 418 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 419 rn, vd, regs, inc, size, align, rm) 420{ 421 %(constructor)s; 422 if (!(condCode == COND_AL || condCode == COND_UC)) { 423 for (int x = 0; x < _numDestRegs; x++) { 424 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 425 } 426 } 427} 428}}; 429 430def template VMemSingleDeclare {{ 431class %(class_name)s : public %(base_class)s 432{ 433 public: 434 // Constructor 435 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 436 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 437 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 438 %(BasicExecPanic)s 439}; 440}}; 441 442def template VMemSingleConstructor {{ 443%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 444 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 445 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 446 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 447 rn, vd, regs, inc, size, align, rm, lane) 448{ 449 %(constructor)s; 450 if (!(condCode == COND_AL || condCode == COND_UC)) { 451 for (int x = 0; x < _numDestRegs; x++) { 452 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 453 } 454 } 455} 456}}; 457 458def template MacroVFPMemDeclare {{ 459/** 460 * Static instructions class for a store multiple instruction 461 */ 462class %(class_name)s : public %(base_class)s 463{ 464 public: 465 // Constructor 466 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 467 RegIndex vd, bool single, bool up, bool writeback, 468 bool load, uint32_t offset); 469 %(BasicExecPanic)s 470}; 471}}; 472 473def template MacroVFPMemConstructor {{ 474%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 475 RegIndex vd, bool single, bool up, bool writeback, bool load, 476 uint32_t offset) 477 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 478 vd, single, up, writeback, load, offset) 479{ 480 %(constructor)s; 481 if (!(condCode == COND_AL || condCode == COND_UC)) { 482 for (int x = 0; x < _numDestRegs; x++) { 483 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 484 } 485 } 486} 487 488}}; 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