1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42// Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49def template MicroMemDeclare {{
50 class %(class_name)s : public %(base_class)s
51 {
52 public:
53 %(class_name)s(ExtMachInst machInst,
54 RegIndex _ura, RegIndex _urb, bool _up,
55 uint8_t _imm);
56 %(BasicExecDeclare)s
57 %(InitiateAccDeclare)s
58 %(CompleteAccDeclare)s
59 };
60}};
61
62def template MicroMemConstructor {{
63 %(class_name)s::%(class_name)s(ExtMachInst machInst,
64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,
67 uint8_t _imm)
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69 _ura, _urb, _up, _imm)
70 {
71 %(constructor)s;
72 if (!(condCode == COND_AL || condCode == COND_UC)) {
73 for (int x = 0; x < _numDestRegs; x++) {
74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
75 }
76 }
77 }
78}};
79
80////////////////////////////////////////////////////////////////////
81//
82// Neon load/store microops
83//
84
85def template MicroNeonMemDeclare {{
86 template <class Element>
87 class %(class_name)s : public %(base_class)s
88 {
89 public:
90 %(class_name)s(ExtMachInst machInst, RegIndex _dest,
91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
92 : %(base_class)s("%(mnemonic)s", machInst,
93 %(op_class)s, _dest, _ura, _imm)
94 {
95 memAccessFlags |= extraMemFlags;
96 %(constructor)s;
97 if (!(condCode == COND_AL || condCode == COND_UC)) {
98 for (int x = 0; x < _numDestRegs; x++) {
99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
100 }
101 }
102 }
103
104 %(BasicExecDeclare)s
105 %(InitiateAccDeclare)s
106 %(CompleteAccDeclare)s
107 };
108}};
109
110////////////////////////////////////////////////////////////////////
111//
|
147// Integer = Integer op Integer microops
148//
149
150def template MicroIntDeclare {{
151 class %(class_name)s : public %(base_class)s
152 {
153 public:
154 %(class_name)s(ExtMachInst machInst,
155 RegIndex _ura, RegIndex _urb, RegIndex _urc);
156 %(BasicExecDeclare)s
157 };
158}};
159
160def template MicroIntConstructor {{
161 %(class_name)s::%(class_name)s(ExtMachInst machInst,
162 RegIndex _ura,
163 RegIndex _urb,
164 RegIndex _urc)
165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
166 _ura, _urb, _urc)
167 {
168 %(constructor)s;
169 if (!(condCode == COND_AL || condCode == COND_UC)) {
170 for (int x = 0; x < _numDestRegs; x++) {
171 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
172 }
173 }
174 }
175}};
176
177def template MicroNeonMemExecDeclare {{
178 template
179 Fault %(class_name)s<%(targs)s>::execute(
180 %(CPU_exec_context)s *, Trace::InstRecord *) const;
181 template
182 Fault %(class_name)s<%(targs)s>::initiateAcc(
183 %(CPU_exec_context)s *, Trace::InstRecord *) const;
184 template
185 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
186 %(CPU_exec_context)s *, Trace::InstRecord *) const;
187}};
188
189def template MicroNeonExecDeclare {{
190 template
191 Fault %(class_name)s<%(targs)s>::execute(
192 %(CPU_exec_context)s *, Trace::InstRecord *) const;
193}};
194
195////////////////////////////////////////////////////////////////////
196//
197// Neon (de)interlacing microops
198//
199
200def template MicroNeonMixDeclare {{
201 template <class Element>
202 class %(class_name)s : public %(base_class)s
203 {
204 public:
205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
206 uint8_t _step) :
207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
208 _dest, _op1, _step)
209 {
210 %(constructor)s;
211 if (!(condCode == COND_AL || condCode == COND_UC)) {
212 for (int x = 0; x < _numDestRegs; x++) {
213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
214 }
215 }
216 }
217
218 %(BasicExecDeclare)s
219 };
220}};
221
222def template MicroNeonMixExecute {{
223 template <class Element>
224 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
225 Trace::InstRecord *traceData) const
226 {
227 Fault fault = NoFault;
228 uint64_t resTemp = 0;
229 resTemp = resTemp;
230 %(op_decl)s;
231 %(op_rd)s;
232
233 if (%(predicate_test)s)
234 {
235 %(code)s;
236 if (fault == NoFault)
237 {
238 %(op_wb)s;
239 }
240 } else {
241 xc->setPredicate(false);
242 }
243
244 if (fault == NoFault && machInst.itstateMask != 0) {
245 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
246 }
247
248 return fault;
249 }
250}};
251
252////////////////////////////////////////////////////////////////////
253//
254// Neon (un)packing microops using a particular lane
255//
256
257def template MicroNeonMixLaneDeclare {{
258 template <class Element>
259 class %(class_name)s : public %(base_class)s
260 {
261 public:
262 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
263 uint8_t _step, unsigned _lane) :
264 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
265 _dest, _op1, _step, _lane)
266 {
267 %(constructor)s;
268 if (!(condCode == COND_AL || condCode == COND_UC)) {
269 for (int x = 0; x < _numDestRegs; x++) {
270 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
271 }
272 }
273 }
274
275 %(BasicExecDeclare)s
276 };
277}};
278
279////////////////////////////////////////////////////////////////////
280//
281// Integer = Integer
282//
283
284def template MicroIntMovDeclare {{
285 class %(class_name)s : public %(base_class)s
286 {
287 public:
288 %(class_name)s(ExtMachInst machInst,
289 RegIndex _ura, RegIndex _urb);
290 %(BasicExecDeclare)s
291 };
292}};
293def template MicroIntMovConstructor {{
294 %(class_name)s::%(class_name)s(ExtMachInst machInst,
295 RegIndex _ura,
296 RegIndex _urb)
297 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
298 _ura, _urb)
299 {
300 %(constructor)s;
301 if (!(condCode == COND_AL || condCode == COND_UC)) {
302 for (int x = 0; x < _numDestRegs; x++) {
303 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
304 }
305 }
306 }
307}};
308
309////////////////////////////////////////////////////////////////////
310//
311// Integer = Integer op Immediate microops
312//
313
314def template MicroIntImmDeclare {{
315 class %(class_name)s : public %(base_class)s
316 {
317 public:
318 %(class_name)s(ExtMachInst machInst,
319 RegIndex _ura, RegIndex _urb,
320 int32_t _imm);
321 %(BasicExecDeclare)s
322 };
323}};
324
325def template MicroIntImmConstructor {{
326 %(class_name)s::%(class_name)s(ExtMachInst machInst,
327 RegIndex _ura,
328 RegIndex _urb,
329 int32_t _imm)
330 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
331 _ura, _urb, _imm)
332 {
333 %(constructor)s;
334 if (!(condCode == COND_AL || condCode == COND_UC)) {
335 for (int x = 0; x < _numDestRegs; x++) {
336 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
337 }
338 }
339 }
340}};
341
342def template MicroIntRegDeclare {{
343 class %(class_name)s : public %(base_class)s
344 {
345 public:
346 %(class_name)s(ExtMachInst machInst,
347 RegIndex _ura, RegIndex _urb, RegIndex _urc,
348 int32_t _shiftAmt, ArmShiftType _shiftType);
349 %(BasicExecDeclare)s
350 };
351}};
352
353def template MicroIntRegConstructor {{
354 %(class_name)s::%(class_name)s(ExtMachInst machInst,
355 RegIndex _ura, RegIndex _urb, RegIndex _urc,
356 int32_t _shiftAmt, ArmShiftType _shiftType)
357 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
358 _ura, _urb, _urc, _shiftAmt, _shiftType)
359 {
360 %(constructor)s;
361 if (!(condCode == COND_AL || condCode == COND_UC)) {
362 for (int x = 0; x < _numDestRegs; x++) {
363 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
364 }
365 }
366 }
367}};
368
369////////////////////////////////////////////////////////////////////
370//
371// Macro Memory-format instructions
372//
373
374def template MacroMemDeclare {{
375/**
376 * Static instructions class for a store multiple instruction
377 */
378class %(class_name)s : public %(base_class)s
379{
380 public:
381 // Constructor
382 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
383 bool index, bool up, bool user, bool writeback, bool load,
384 uint32_t reglist);
385 %(BasicExecPanic)s
386};
387}};
388
389def template MacroMemConstructor {{
390%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
391 bool index, bool up, bool user, bool writeback, bool load,
392 uint32_t reglist)
393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
394 index, up, user, writeback, load, reglist)
395{
396 %(constructor)s;
397 if (!(condCode == COND_AL || condCode == COND_UC)) {
398 for (int x = 0; x < _numDestRegs; x++) {
399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
400 }
401 }
402}
403
404}};
405
406def template VMemMultDeclare {{
407class %(class_name)s : public %(base_class)s
408{
409 public:
410 // Constructor
411 %(class_name)s(ExtMachInst machInst, unsigned width,
412 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
413 uint32_t size, uint32_t align, RegIndex rm);
414 %(BasicExecPanic)s
415};
416}};
417
418def template VMemMultConstructor {{
419%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
420 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
421 uint32_t size, uint32_t align, RegIndex rm)
422 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
423 rn, vd, regs, inc, size, align, rm)
424{
425 %(constructor)s;
426 if (!(condCode == COND_AL || condCode == COND_UC)) {
427 for (int x = 0; x < _numDestRegs; x++) {
428 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
429 }
430 }
431}
432}};
433
434def template VMemSingleDeclare {{
435class %(class_name)s : public %(base_class)s
436{
437 public:
438 // Constructor
439 %(class_name)s(ExtMachInst machInst, bool all, unsigned width,
440 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
441 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
442 %(BasicExecPanic)s
443};
444}};
445
446def template VMemSingleConstructor {{
447%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
448 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
449 uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
450 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
451 rn, vd, regs, inc, size, align, rm, lane)
452{
453 %(constructor)s;
454 if (!(condCode == COND_AL || condCode == COND_UC)) {
455 for (int x = 0; x < _numDestRegs; x++) {
456 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
457 }
458 }
459}
460}};
461
462def template MacroVFPMemDeclare {{
463/**
464 * Static instructions class for a store multiple instruction
465 */
466class %(class_name)s : public %(base_class)s
467{
468 public:
469 // Constructor
470 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
471 RegIndex vd, bool single, bool up, bool writeback,
472 bool load, uint32_t offset);
473 %(BasicExecPanic)s
474};
475}};
476
477def template MacroVFPMemConstructor {{
478%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
479 RegIndex vd, bool single, bool up, bool writeback, bool load,
480 uint32_t offset)
481 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
482 vd, single, up, writeback, load, offset)
483{
484 %(constructor)s;
485 if (!(condCode == COND_AL || condCode == COND_UC)) {
486 for (int x = 0; x < _numDestRegs; x++) {
487 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
488 }
489 }
490}
491
492}};
|