1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42// Gabe Black 43 44//////////////////////////////////////////////////////////////////// 45// 46// Load/store microops 47// 48 49def template MicroMemDeclare {{ 50 class %(class_name)s : public %(base_class)s 51 { 52 public: 53 %(class_name)s(ExtMachInst machInst, 54 RegIndex _ura, RegIndex _urb, bool _up, 55 uint8_t _imm); 56 %(BasicExecDeclare)s 57 %(InitiateAccDeclare)s 58 %(CompleteAccDeclare)s 59 }; 60}}; 61 62def template MicroMemConstructor {{ 63 %(class_name)s::%(class_name)s(ExtMachInst machInst, 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 if (!(condCode == COND_AL || condCode == COND_UC)) { 73 for (int x = 0; x < _numDestRegs; x++) { 74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 75 } 76 } 77 } 78}}; 79 80//////////////////////////////////////////////////////////////////// 81// 82// Neon load/store microops 83// 84 85def template MicroNeonMemDeclare {{ 86 template <class Element> 87 class %(class_name)s : public %(base_class)s 88 { 89 public: 90 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 92 : %(base_class)s("%(mnemonic)s", machInst, 93 %(op_class)s, _dest, _ura, _imm) 94 { 95 memAccessFlags |= extraMemFlags; 96 %(constructor)s; 97 if (!(condCode == COND_AL || condCode == COND_UC)) { 98 for (int x = 0; x < _numDestRegs; x++) { 99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 100 } 101 } 102 } 103 104 %(BasicExecDeclare)s 105 %(InitiateAccDeclare)s 106 %(CompleteAccDeclare)s 107 }; 108}}; 109 110//////////////////////////////////////////////////////////////////// 111//
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42// Gabe Black 43 44//////////////////////////////////////////////////////////////////// 45// 46// Load/store microops 47// 48 49def template MicroMemDeclare {{ 50 class %(class_name)s : public %(base_class)s 51 { 52 public: 53 %(class_name)s(ExtMachInst machInst, 54 RegIndex _ura, RegIndex _urb, bool _up, 55 uint8_t _imm); 56 %(BasicExecDeclare)s 57 %(InitiateAccDeclare)s 58 %(CompleteAccDeclare)s 59 }; 60}}; 61 62def template MicroMemConstructor {{ 63 %(class_name)s::%(class_name)s(ExtMachInst machInst, 64 RegIndex _ura, 65 RegIndex _urb, 66 bool _up, 67 uint8_t _imm) 68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 69 _ura, _urb, _up, _imm) 70 { 71 %(constructor)s; 72 if (!(condCode == COND_AL || condCode == COND_UC)) { 73 for (int x = 0; x < _numDestRegs; x++) { 74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 75 } 76 } 77 } 78}}; 79 80//////////////////////////////////////////////////////////////////// 81// 82// Neon load/store microops 83// 84 85def template MicroNeonMemDeclare {{ 86 template <class Element> 87 class %(class_name)s : public %(base_class)s 88 { 89 public: 90 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 92 : %(base_class)s("%(mnemonic)s", machInst, 93 %(op_class)s, _dest, _ura, _imm) 94 { 95 memAccessFlags |= extraMemFlags; 96 %(constructor)s; 97 if (!(condCode == COND_AL || condCode == COND_UC)) { 98 for (int x = 0; x < _numDestRegs; x++) { 99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 100 } 101 } 102 } 103 104 %(BasicExecDeclare)s 105 %(InitiateAccDeclare)s 106 %(CompleteAccDeclare)s 107 }; 108}}; 109 110//////////////////////////////////////////////////////////////////// 111//
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112// Integer = Integer op Integer microops 113// 114 115def template MicroIntDeclare {{ 116 class %(class_name)s : public %(base_class)s 117 { 118 public: 119 %(class_name)s(ExtMachInst machInst, 120 RegIndex _ura, RegIndex _urb, RegIndex _urc); 121 %(BasicExecDeclare)s 122 }; 123}}; 124 125def template MicroIntConstructor {{ 126 %(class_name)s::%(class_name)s(ExtMachInst machInst, 127 RegIndex _ura, 128 RegIndex _urb, 129 RegIndex _urc) 130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 131 _ura, _urb, _urc) 132 { 133 %(constructor)s; 134 if (!(condCode == COND_AL || condCode == COND_UC)) { 135 for (int x = 0; x < _numDestRegs; x++) { 136 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 137 } 138 } 139 } 140}}; 141 142def template MicroNeonMemExecDeclare {{ 143 template 144 Fault %(class_name)s<%(targs)s>::execute( 145 %(CPU_exec_context)s *, Trace::InstRecord *) const; 146 template 147 Fault %(class_name)s<%(targs)s>::initiateAcc( 148 %(CPU_exec_context)s *, Trace::InstRecord *) const; 149 template 150 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 151 %(CPU_exec_context)s *, Trace::InstRecord *) const; 152}}; 153 154def template MicroNeonExecDeclare {{ 155 template 156 Fault %(class_name)s<%(targs)s>::execute( 157 %(CPU_exec_context)s *, Trace::InstRecord *) const; 158}}; 159 160//////////////////////////////////////////////////////////////////// 161// 162// Neon (de)interlacing microops 163// 164 165def template MicroNeonMixDeclare {{ 166 template <class Element> 167 class %(class_name)s : public %(base_class)s 168 { 169 public: 170 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 171 uint8_t _step) : 172 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 173 _dest, _op1, _step) 174 { 175 %(constructor)s; 176 if (!(condCode == COND_AL || condCode == COND_UC)) { 177 for (int x = 0; x < _numDestRegs; x++) { 178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 179 } 180 } 181 } 182 183 %(BasicExecDeclare)s 184 }; 185}}; 186 187def template MicroNeonMixExecute {{ 188 template <class Element> 189 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 190 Trace::InstRecord *traceData) const 191 { 192 Fault fault = NoFault; 193 uint64_t resTemp = 0; 194 resTemp = resTemp; 195 %(op_decl)s; 196 %(op_rd)s; 197 198 if (%(predicate_test)s) 199 { 200 %(code)s; 201 if (fault == NoFault) 202 { 203 %(op_wb)s; 204 } 205 } else { 206 xc->setPredicate(false); 207 } 208 209 if (fault == NoFault && machInst.itstateMask != 0) { 210 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 211 } 212 213 return fault; 214 } 215}}; 216 217//////////////////////////////////////////////////////////////////// 218// 219// Neon (un)packing microops using a particular lane 220// 221 222def template MicroNeonMixLaneDeclare {{ 223 template <class Element> 224 class %(class_name)s : public %(base_class)s 225 { 226 public: 227 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 228 uint8_t _step, unsigned _lane) : 229 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 230 _dest, _op1, _step, _lane) 231 { 232 %(constructor)s; 233 if (!(condCode == COND_AL || condCode == COND_UC)) { 234 for (int x = 0; x < _numDestRegs; x++) { 235 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 236 } 237 } 238 } 239 240 %(BasicExecDeclare)s 241 }; 242}}; 243 244//////////////////////////////////////////////////////////////////// 245// 246// Integer = Integer 247// 248 249def template MicroIntMovDeclare {{ 250 class %(class_name)s : public %(base_class)s 251 { 252 public: 253 %(class_name)s(ExtMachInst machInst, 254 RegIndex _ura, RegIndex _urb); 255 %(BasicExecDeclare)s 256 }; 257}}; 258def template MicroIntMovConstructor {{ 259 %(class_name)s::%(class_name)s(ExtMachInst machInst, 260 RegIndex _ura, 261 RegIndex _urb) 262 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 263 _ura, _urb) 264 { 265 %(constructor)s; 266 if (!(condCode == COND_AL || condCode == COND_UC)) { 267 for (int x = 0; x < _numDestRegs; x++) { 268 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 269 } 270 } 271 } 272}}; 273 274//////////////////////////////////////////////////////////////////// 275// 276// Integer = Integer op Immediate microops 277// 278 279def template MicroIntImmDeclare {{ 280 class %(class_name)s : public %(base_class)s 281 { 282 public: 283 %(class_name)s(ExtMachInst machInst, 284 RegIndex _ura, RegIndex _urb, 285 int32_t _imm); 286 %(BasicExecDeclare)s 287 }; 288}}; 289 290def template MicroIntImmConstructor {{ 291 %(class_name)s::%(class_name)s(ExtMachInst machInst, 292 RegIndex _ura, 293 RegIndex _urb, 294 int32_t _imm) 295 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 296 _ura, _urb, _imm) 297 { 298 %(constructor)s; 299 if (!(condCode == COND_AL || condCode == COND_UC)) { 300 for (int x = 0; x < _numDestRegs; x++) { 301 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 302 } 303 } 304 } 305}}; 306 307def template MicroIntRegDeclare {{ 308 class %(class_name)s : public %(base_class)s 309 { 310 public: 311 %(class_name)s(ExtMachInst machInst, 312 RegIndex _ura, RegIndex _urb, RegIndex _urc, 313 int32_t _shiftAmt, ArmShiftType _shiftType); 314 %(BasicExecDeclare)s 315 }; 316}}; 317 318def template MicroIntRegConstructor {{ 319 %(class_name)s::%(class_name)s(ExtMachInst machInst, 320 RegIndex _ura, RegIndex _urb, RegIndex _urc, 321 int32_t _shiftAmt, ArmShiftType _shiftType) 322 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 323 _ura, _urb, _urc, _shiftAmt, _shiftType) 324 { 325 %(constructor)s; 326 if (!(condCode == COND_AL || condCode == COND_UC)) { 327 for (int x = 0; x < _numDestRegs; x++) { 328 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 329 } 330 } 331 } 332}}; 333 334//////////////////////////////////////////////////////////////////// 335// 336// Macro Memory-format instructions 337// 338 339def template MacroMemDeclare {{ 340/** 341 * Static instructions class for a store multiple instruction 342 */ 343class %(class_name)s : public %(base_class)s 344{ 345 public: 346 // Constructor 347 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 348 bool index, bool up, bool user, bool writeback, bool load, 349 uint32_t reglist); 350 %(BasicExecPanic)s 351}; 352}}; 353 354def template MacroMemConstructor {{ 355%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 356 bool index, bool up, bool user, bool writeback, bool load, 357 uint32_t reglist) 358 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 359 index, up, user, writeback, load, reglist) 360{ 361 %(constructor)s; 362 if (!(condCode == COND_AL || condCode == COND_UC)) { 363 for (int x = 0; x < _numDestRegs; x++) { 364 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 365 } 366 } 367} 368 369}}; 370 371def template VMemMultDeclare {{ 372class %(class_name)s : public %(base_class)s 373{ 374 public: 375 // Constructor 376 %(class_name)s(ExtMachInst machInst, unsigned width, 377 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 378 uint32_t size, uint32_t align, RegIndex rm); 379 %(BasicExecPanic)s 380}; 381}}; 382 383def template VMemMultConstructor {{ 384%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 385 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 386 uint32_t size, uint32_t align, RegIndex rm) 387 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 388 rn, vd, regs, inc, size, align, rm) 389{ 390 %(constructor)s; 391 if (!(condCode == COND_AL || condCode == COND_UC)) { 392 for (int x = 0; x < _numDestRegs; x++) { 393 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 394 } 395 } 396} 397}}; 398 399def template VMemSingleDeclare {{ 400class %(class_name)s : public %(base_class)s 401{ 402 public: 403 // Constructor 404 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 405 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 406 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 407 %(BasicExecPanic)s 408}; 409}}; 410 411def template VMemSingleConstructor {{ 412%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 413 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 414 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 415 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 416 rn, vd, regs, inc, size, align, rm, lane) 417{ 418 %(constructor)s; 419 if (!(condCode == COND_AL || condCode == COND_UC)) { 420 for (int x = 0; x < _numDestRegs; x++) { 421 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 422 } 423 } 424} 425}}; 426 427def template MacroVFPMemDeclare {{ 428/** 429 * Static instructions class for a store multiple instruction 430 */ 431class %(class_name)s : public %(base_class)s 432{ 433 public: 434 // Constructor 435 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 436 RegIndex vd, bool single, bool up, bool writeback, 437 bool load, uint32_t offset); 438 %(BasicExecPanic)s 439}; 440}}; 441 442def template MacroVFPMemConstructor {{ 443%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 444 RegIndex vd, bool single, bool up, bool writeback, bool load, 445 uint32_t offset) 446 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 447 vd, single, up, writeback, load, offset) 448{ 449 %(constructor)s; 450 if (!(condCode == COND_AL || condCode == COND_UC)) { 451 for (int x = 0; x < _numDestRegs; x++) { 452 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 453 } 454 } 455} 456 457}};
| 147// Integer = Integer op Integer microops 148// 149 150def template MicroIntDeclare {{ 151 class %(class_name)s : public %(base_class)s 152 { 153 public: 154 %(class_name)s(ExtMachInst machInst, 155 RegIndex _ura, RegIndex _urb, RegIndex _urc); 156 %(BasicExecDeclare)s 157 }; 158}}; 159 160def template MicroIntConstructor {{ 161 %(class_name)s::%(class_name)s(ExtMachInst machInst, 162 RegIndex _ura, 163 RegIndex _urb, 164 RegIndex _urc) 165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 166 _ura, _urb, _urc) 167 { 168 %(constructor)s; 169 if (!(condCode == COND_AL || condCode == COND_UC)) { 170 for (int x = 0; x < _numDestRegs; x++) { 171 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 172 } 173 } 174 } 175}}; 176 177def template MicroNeonMemExecDeclare {{ 178 template 179 Fault %(class_name)s<%(targs)s>::execute( 180 %(CPU_exec_context)s *, Trace::InstRecord *) const; 181 template 182 Fault %(class_name)s<%(targs)s>::initiateAcc( 183 %(CPU_exec_context)s *, Trace::InstRecord *) const; 184 template 185 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 186 %(CPU_exec_context)s *, Trace::InstRecord *) const; 187}}; 188 189def template MicroNeonExecDeclare {{ 190 template 191 Fault %(class_name)s<%(targs)s>::execute( 192 %(CPU_exec_context)s *, Trace::InstRecord *) const; 193}}; 194 195//////////////////////////////////////////////////////////////////// 196// 197// Neon (de)interlacing microops 198// 199 200def template MicroNeonMixDeclare {{ 201 template <class Element> 202 class %(class_name)s : public %(base_class)s 203 { 204 public: 205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 206 uint8_t _step) : 207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 208 _dest, _op1, _step) 209 { 210 %(constructor)s; 211 if (!(condCode == COND_AL || condCode == COND_UC)) { 212 for (int x = 0; x < _numDestRegs; x++) { 213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 214 } 215 } 216 } 217 218 %(BasicExecDeclare)s 219 }; 220}}; 221 222def template MicroNeonMixExecute {{ 223 template <class Element> 224 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 225 Trace::InstRecord *traceData) const 226 { 227 Fault fault = NoFault; 228 uint64_t resTemp = 0; 229 resTemp = resTemp; 230 %(op_decl)s; 231 %(op_rd)s; 232 233 if (%(predicate_test)s) 234 { 235 %(code)s; 236 if (fault == NoFault) 237 { 238 %(op_wb)s; 239 } 240 } else { 241 xc->setPredicate(false); 242 } 243 244 if (fault == NoFault && machInst.itstateMask != 0) { 245 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 246 } 247 248 return fault; 249 } 250}}; 251 252//////////////////////////////////////////////////////////////////// 253// 254// Neon (un)packing microops using a particular lane 255// 256 257def template MicroNeonMixLaneDeclare {{ 258 template <class Element> 259 class %(class_name)s : public %(base_class)s 260 { 261 public: 262 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 263 uint8_t _step, unsigned _lane) : 264 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 265 _dest, _op1, _step, _lane) 266 { 267 %(constructor)s; 268 if (!(condCode == COND_AL || condCode == COND_UC)) { 269 for (int x = 0; x < _numDestRegs; x++) { 270 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 271 } 272 } 273 } 274 275 %(BasicExecDeclare)s 276 }; 277}}; 278 279//////////////////////////////////////////////////////////////////// 280// 281// Integer = Integer 282// 283 284def template MicroIntMovDeclare {{ 285 class %(class_name)s : public %(base_class)s 286 { 287 public: 288 %(class_name)s(ExtMachInst machInst, 289 RegIndex _ura, RegIndex _urb); 290 %(BasicExecDeclare)s 291 }; 292}}; 293def template MicroIntMovConstructor {{ 294 %(class_name)s::%(class_name)s(ExtMachInst machInst, 295 RegIndex _ura, 296 RegIndex _urb) 297 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 298 _ura, _urb) 299 { 300 %(constructor)s; 301 if (!(condCode == COND_AL || condCode == COND_UC)) { 302 for (int x = 0; x < _numDestRegs; x++) { 303 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 304 } 305 } 306 } 307}}; 308 309//////////////////////////////////////////////////////////////////// 310// 311// Integer = Integer op Immediate microops 312// 313 314def template MicroIntImmDeclare {{ 315 class %(class_name)s : public %(base_class)s 316 { 317 public: 318 %(class_name)s(ExtMachInst machInst, 319 RegIndex _ura, RegIndex _urb, 320 int32_t _imm); 321 %(BasicExecDeclare)s 322 }; 323}}; 324 325def template MicroIntImmConstructor {{ 326 %(class_name)s::%(class_name)s(ExtMachInst machInst, 327 RegIndex _ura, 328 RegIndex _urb, 329 int32_t _imm) 330 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 331 _ura, _urb, _imm) 332 { 333 %(constructor)s; 334 if (!(condCode == COND_AL || condCode == COND_UC)) { 335 for (int x = 0; x < _numDestRegs; x++) { 336 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 337 } 338 } 339 } 340}}; 341 342def template MicroIntRegDeclare {{ 343 class %(class_name)s : public %(base_class)s 344 { 345 public: 346 %(class_name)s(ExtMachInst machInst, 347 RegIndex _ura, RegIndex _urb, RegIndex _urc, 348 int32_t _shiftAmt, ArmShiftType _shiftType); 349 %(BasicExecDeclare)s 350 }; 351}}; 352 353def template MicroIntRegConstructor {{ 354 %(class_name)s::%(class_name)s(ExtMachInst machInst, 355 RegIndex _ura, RegIndex _urb, RegIndex _urc, 356 int32_t _shiftAmt, ArmShiftType _shiftType) 357 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 358 _ura, _urb, _urc, _shiftAmt, _shiftType) 359 { 360 %(constructor)s; 361 if (!(condCode == COND_AL || condCode == COND_UC)) { 362 for (int x = 0; x < _numDestRegs; x++) { 363 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 364 } 365 } 366 } 367}}; 368 369//////////////////////////////////////////////////////////////////// 370// 371// Macro Memory-format instructions 372// 373 374def template MacroMemDeclare {{ 375/** 376 * Static instructions class for a store multiple instruction 377 */ 378class %(class_name)s : public %(base_class)s 379{ 380 public: 381 // Constructor 382 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 383 bool index, bool up, bool user, bool writeback, bool load, 384 uint32_t reglist); 385 %(BasicExecPanic)s 386}; 387}}; 388 389def template MacroMemConstructor {{ 390%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 391 bool index, bool up, bool user, bool writeback, bool load, 392 uint32_t reglist) 393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 394 index, up, user, writeback, load, reglist) 395{ 396 %(constructor)s; 397 if (!(condCode == COND_AL || condCode == COND_UC)) { 398 for (int x = 0; x < _numDestRegs; x++) { 399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 400 } 401 } 402} 403 404}}; 405 406def template VMemMultDeclare {{ 407class %(class_name)s : public %(base_class)s 408{ 409 public: 410 // Constructor 411 %(class_name)s(ExtMachInst machInst, unsigned width, 412 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 413 uint32_t size, uint32_t align, RegIndex rm); 414 %(BasicExecPanic)s 415}; 416}}; 417 418def template VMemMultConstructor {{ 419%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 420 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 421 uint32_t size, uint32_t align, RegIndex rm) 422 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 423 rn, vd, regs, inc, size, align, rm) 424{ 425 %(constructor)s; 426 if (!(condCode == COND_AL || condCode == COND_UC)) { 427 for (int x = 0; x < _numDestRegs; x++) { 428 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 429 } 430 } 431} 432}}; 433 434def template VMemSingleDeclare {{ 435class %(class_name)s : public %(base_class)s 436{ 437 public: 438 // Constructor 439 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 440 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 441 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 442 %(BasicExecPanic)s 443}; 444}}; 445 446def template VMemSingleConstructor {{ 447%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 448 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 449 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 450 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 451 rn, vd, regs, inc, size, align, rm, lane) 452{ 453 %(constructor)s; 454 if (!(condCode == COND_AL || condCode == COND_UC)) { 455 for (int x = 0; x < _numDestRegs; x++) { 456 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 457 } 458 } 459} 460}}; 461 462def template MacroVFPMemDeclare {{ 463/** 464 * Static instructions class for a store multiple instruction 465 */ 466class %(class_name)s : public %(base_class)s 467{ 468 public: 469 // Constructor 470 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 471 RegIndex vd, bool single, bool up, bool writeback, 472 bool load, uint32_t offset); 473 %(BasicExecPanic)s 474}; 475}}; 476 477def template MacroVFPMemConstructor {{ 478%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 479 RegIndex vd, bool single, bool up, bool writeback, bool load, 480 uint32_t offset) 481 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 482 vd, single, up, writeback, load, offset) 483{ 484 %(constructor)s; 485 if (!(condCode == COND_AL || condCode == COND_UC)) { 486 for (int x = 0; x < _numDestRegs; x++) { 487 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 488 } 489 } 490} 491 492}};
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