1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42// Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49def template MicroMemDeclare {{
50 class %(class_name)s : public %(base_class)s
51 {
52 public:
53 %(class_name)s(ExtMachInst machInst,
54 RegIndex _ura, RegIndex _urb, bool _up,
55 uint8_t _imm);
56 %(BasicExecDeclare)s
57 %(InitiateAccDeclare)s
58 %(CompleteAccDeclare)s
59 };
60}};
61
62def template MicroMemConstructor {{
63 %(class_name)s::%(class_name)s(ExtMachInst machInst,
64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,
67 uint8_t _imm)
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69 _ura, _urb, _up, _imm)
70 {
71 %(constructor)s;
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42// Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49def template MicroMemDeclare {{
50 class %(class_name)s : public %(base_class)s
51 {
52 public:
53 %(class_name)s(ExtMachInst machInst,
54 RegIndex _ura, RegIndex _urb, bool _up,
55 uint8_t _imm);
56 %(BasicExecDeclare)s
57 %(InitiateAccDeclare)s
58 %(CompleteAccDeclare)s
59 };
60}};
61
62def template MicroMemConstructor {{
63 %(class_name)s::%(class_name)s(ExtMachInst machInst,
64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,
67 uint8_t _imm)
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69 _ura, _urb, _up, _imm)
70 {
71 %(constructor)s;
|
| 72 if (!(condCode == COND_AL || condCode == COND_UC)) {
73 for (int x = 0; x < _numDestRegs; x++) {
74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
75 }
76 }
|
72 }
73}};
74
75////////////////////////////////////////////////////////////////////
76//
77// Neon load/store microops
78//
79
80def template MicroNeonMemDeclare {{
81 template <class Element>
82 class %(class_name)s : public %(base_class)s
83 {
84 public:
85 %(class_name)s(ExtMachInst machInst, RegIndex _dest,
86 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
87 : %(base_class)s("%(mnemonic)s", machInst,
88 %(op_class)s, _dest, _ura, _imm)
89 {
90 memAccessFlags |= extraMemFlags;
91 %(constructor)s;
| 77 }
78}};
79
80////////////////////////////////////////////////////////////////////
81//
82// Neon load/store microops
83//
84
85def template MicroNeonMemDeclare {{
86 template <class Element>
87 class %(class_name)s : public %(base_class)s
88 {
89 public:
90 %(class_name)s(ExtMachInst machInst, RegIndex _dest,
91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
92 : %(base_class)s("%(mnemonic)s", machInst,
93 %(op_class)s, _dest, _ura, _imm)
94 {
95 memAccessFlags |= extraMemFlags;
96 %(constructor)s;
|
| 97 if (!(condCode == COND_AL || condCode == COND_UC)) {
98 for (int x = 0; x < _numDestRegs; x++) {
99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
100 }
101 }
|
92 }
93
94 %(BasicExecDeclare)s
95 %(InitiateAccDeclare)s
96 %(CompleteAccDeclare)s
97 };
98}};
99
100////////////////////////////////////////////////////////////////////
101//
102// Integer = Integer op Integer microops
103//
104
105def template MicroIntDeclare {{
106 class %(class_name)s : public %(base_class)s
107 {
108 public:
109 %(class_name)s(ExtMachInst machInst,
110 RegIndex _ura, RegIndex _urb, RegIndex _urc);
111 %(BasicExecDeclare)s
112 };
113}};
114
115def template MicroIntConstructor {{
116 %(class_name)s::%(class_name)s(ExtMachInst machInst,
117 RegIndex _ura,
118 RegIndex _urb,
119 RegIndex _urc)
120 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
121 _ura, _urb, _urc)
122 {
123 %(constructor)s;
| 102 }
103
104 %(BasicExecDeclare)s
105 %(InitiateAccDeclare)s
106 %(CompleteAccDeclare)s
107 };
108}};
109
110////////////////////////////////////////////////////////////////////
111//
112// Integer = Integer op Integer microops
113//
114
115def template MicroIntDeclare {{
116 class %(class_name)s : public %(base_class)s
117 {
118 public:
119 %(class_name)s(ExtMachInst machInst,
120 RegIndex _ura, RegIndex _urb, RegIndex _urc);
121 %(BasicExecDeclare)s
122 };
123}};
124
125def template MicroIntConstructor {{
126 %(class_name)s::%(class_name)s(ExtMachInst machInst,
127 RegIndex _ura,
128 RegIndex _urb,
129 RegIndex _urc)
130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
131 _ura, _urb, _urc)
132 {
133 %(constructor)s;
|
| 134 if (!(condCode == COND_AL || condCode == COND_UC)) {
135 for (int x = 0; x < _numDestRegs; x++) {
136 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
137 }
138 }
|
124 }
125}};
126
127def template MicroNeonMemExecDeclare {{
128 template
129 Fault %(class_name)s<%(targs)s>::execute(
130 %(CPU_exec_context)s *, Trace::InstRecord *) const;
131 template
132 Fault %(class_name)s<%(targs)s>::initiateAcc(
133 %(CPU_exec_context)s *, Trace::InstRecord *) const;
134 template
135 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
136 %(CPU_exec_context)s *, Trace::InstRecord *) const;
137}};
138
139def template MicroNeonExecDeclare {{
140 template
141 Fault %(class_name)s<%(targs)s>::execute(
142 %(CPU_exec_context)s *, Trace::InstRecord *) const;
143}};
144
145////////////////////////////////////////////////////////////////////
146//
147// Neon (de)interlacing microops
148//
149
150def template MicroNeonMixDeclare {{
151 template <class Element>
152 class %(class_name)s : public %(base_class)s
153 {
154 public:
155 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
156 uint8_t _step) :
157 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
158 _dest, _op1, _step)
159 {
160 %(constructor)s;
| 139 }
140}};
141
142def template MicroNeonMemExecDeclare {{
143 template
144 Fault %(class_name)s<%(targs)s>::execute(
145 %(CPU_exec_context)s *, Trace::InstRecord *) const;
146 template
147 Fault %(class_name)s<%(targs)s>::initiateAcc(
148 %(CPU_exec_context)s *, Trace::InstRecord *) const;
149 template
150 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
151 %(CPU_exec_context)s *, Trace::InstRecord *) const;
152}};
153
154def template MicroNeonExecDeclare {{
155 template
156 Fault %(class_name)s<%(targs)s>::execute(
157 %(CPU_exec_context)s *, Trace::InstRecord *) const;
158}};
159
160////////////////////////////////////////////////////////////////////
161//
162// Neon (de)interlacing microops
163//
164
165def template MicroNeonMixDeclare {{
166 template <class Element>
167 class %(class_name)s : public %(base_class)s
168 {
169 public:
170 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
171 uint8_t _step) :
172 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
173 _dest, _op1, _step)
174 {
175 %(constructor)s;
|
| 176 if (!(condCode == COND_AL || condCode == COND_UC)) {
177 for (int x = 0; x < _numDestRegs; x++) {
178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
179 }
180 }
|
161 }
162
163 %(BasicExecDeclare)s
164 };
165}};
166
167def template MicroNeonMixExecute {{
168 template <class Element>
169 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
170 Trace::InstRecord *traceData) const
171 {
172 Fault fault = NoFault;
173 uint64_t resTemp = 0;
174 resTemp = resTemp;
175 %(op_decl)s;
176 %(op_rd)s;
177
178 if (%(predicate_test)s)
179 {
180 %(code)s;
181 if (fault == NoFault)
182 {
183 %(op_wb)s;
184 }
185 }
186
187 if (fault == NoFault && machInst.itstateMask != 0) {
188 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
189 }
190
191 return fault;
192 }
193}};
194
195////////////////////////////////////////////////////////////////////
196//
197// Neon (un)packing microops using a particular lane
198//
199
200def template MicroNeonMixLaneDeclare {{
201 template <class Element>
202 class %(class_name)s : public %(base_class)s
203 {
204 public:
205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
206 uint8_t _step, unsigned _lane) :
207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
208 _dest, _op1, _step, _lane)
209 {
210 %(constructor)s;
| 181 }
182
183 %(BasicExecDeclare)s
184 };
185}};
186
187def template MicroNeonMixExecute {{
188 template <class Element>
189 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
190 Trace::InstRecord *traceData) const
191 {
192 Fault fault = NoFault;
193 uint64_t resTemp = 0;
194 resTemp = resTemp;
195 %(op_decl)s;
196 %(op_rd)s;
197
198 if (%(predicate_test)s)
199 {
200 %(code)s;
201 if (fault == NoFault)
202 {
203 %(op_wb)s;
204 }
205 }
206
207 if (fault == NoFault && machInst.itstateMask != 0) {
208 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
209 }
210
211 return fault;
212 }
213}};
214
215////////////////////////////////////////////////////////////////////
216//
217// Neon (un)packing microops using a particular lane
218//
219
220def template MicroNeonMixLaneDeclare {{
221 template <class Element>
222 class %(class_name)s : public %(base_class)s
223 {
224 public:
225 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
226 uint8_t _step, unsigned _lane) :
227 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
228 _dest, _op1, _step, _lane)
229 {
230 %(constructor)s;
|
| 231 if (!(condCode == COND_AL || condCode == COND_UC)) {
232 for (int x = 0; x < _numDestRegs; x++) {
233 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
234 }
235 }
|
211 }
212
213 %(BasicExecDeclare)s
214 };
215}};
216
217////////////////////////////////////////////////////////////////////
218//
219// Integer = Integer
220//
221
222def template MicroIntMovDeclare {{
223 class %(class_name)s : public %(base_class)s
224 {
225 public:
226 %(class_name)s(ExtMachInst machInst,
227 RegIndex _ura, RegIndex _urb);
228 %(BasicExecDeclare)s
229 };
230}};
231def template MicroIntMovConstructor {{
232 %(class_name)s::%(class_name)s(ExtMachInst machInst,
233 RegIndex _ura,
234 RegIndex _urb)
235 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
236 _ura, _urb)
237 {
238 %(constructor)s;
| 236 }
237
238 %(BasicExecDeclare)s
239 };
240}};
241
242////////////////////////////////////////////////////////////////////
243//
244// Integer = Integer
245//
246
247def template MicroIntMovDeclare {{
248 class %(class_name)s : public %(base_class)s
249 {
250 public:
251 %(class_name)s(ExtMachInst machInst,
252 RegIndex _ura, RegIndex _urb);
253 %(BasicExecDeclare)s
254 };
255}};
256def template MicroIntMovConstructor {{
257 %(class_name)s::%(class_name)s(ExtMachInst machInst,
258 RegIndex _ura,
259 RegIndex _urb)
260 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
261 _ura, _urb)
262 {
263 %(constructor)s;
|
| 264 if (!(condCode == COND_AL || condCode == COND_UC)) {
265 for (int x = 0; x < _numDestRegs; x++) {
266 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
267 }
268 }
|
239 }
240}};
241
242////////////////////////////////////////////////////////////////////
243//
244// Integer = Integer op Immediate microops
245//
246
247def template MicroIntImmDeclare {{
248 class %(class_name)s : public %(base_class)s
249 {
250 public:
251 %(class_name)s(ExtMachInst machInst,
252 RegIndex _ura, RegIndex _urb,
253 int32_t _imm);
254 %(BasicExecDeclare)s
255 };
256}};
257
258def template MicroIntImmConstructor {{
259 %(class_name)s::%(class_name)s(ExtMachInst machInst,
260 RegIndex _ura,
261 RegIndex _urb,
262 int32_t _imm)
263 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
264 _ura, _urb, _imm)
265 {
266 %(constructor)s;
| 269 }
270}};
271
272////////////////////////////////////////////////////////////////////
273//
274// Integer = Integer op Immediate microops
275//
276
277def template MicroIntImmDeclare {{
278 class %(class_name)s : public %(base_class)s
279 {
280 public:
281 %(class_name)s(ExtMachInst machInst,
282 RegIndex _ura, RegIndex _urb,
283 int32_t _imm);
284 %(BasicExecDeclare)s
285 };
286}};
287
288def template MicroIntImmConstructor {{
289 %(class_name)s::%(class_name)s(ExtMachInst machInst,
290 RegIndex _ura,
291 RegIndex _urb,
292 int32_t _imm)
293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
294 _ura, _urb, _imm)
295 {
296 %(constructor)s;
|
| 297 if (!(condCode == COND_AL || condCode == COND_UC)) {
298 for (int x = 0; x < _numDestRegs; x++) {
299 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
300 }
301 }
|
267 }
268}};
269
270def template MicroIntRegDeclare {{
271 class %(class_name)s : public %(base_class)s
272 {
273 public:
274 %(class_name)s(ExtMachInst machInst,
275 RegIndex _ura, RegIndex _urb, RegIndex _urc,
276 int32_t _shiftAmt, ArmShiftType _shiftType);
277 %(BasicExecDeclare)s
278 };
279}};
280
281def template MicroIntRegConstructor {{
282 %(class_name)s::%(class_name)s(ExtMachInst machInst,
283 RegIndex _ura, RegIndex _urb, RegIndex _urc,
284 int32_t _shiftAmt, ArmShiftType _shiftType)
285 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
286 _ura, _urb, _urc, _shiftAmt, _shiftType)
287 {
288 %(constructor)s;
| 302 }
303}};
304
305def template MicroIntRegDeclare {{
306 class %(class_name)s : public %(base_class)s
307 {
308 public:
309 %(class_name)s(ExtMachInst machInst,
310 RegIndex _ura, RegIndex _urb, RegIndex _urc,
311 int32_t _shiftAmt, ArmShiftType _shiftType);
312 %(BasicExecDeclare)s
313 };
314}};
315
316def template MicroIntRegConstructor {{
317 %(class_name)s::%(class_name)s(ExtMachInst machInst,
318 RegIndex _ura, RegIndex _urb, RegIndex _urc,
319 int32_t _shiftAmt, ArmShiftType _shiftType)
320 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
321 _ura, _urb, _urc, _shiftAmt, _shiftType)
322 {
323 %(constructor)s;
|
| 324 if (!(condCode == COND_AL || condCode == COND_UC)) {
325 for (int x = 0; x < _numDestRegs; x++) {
326 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
327 }
328 }
|
289 }
290}};
291
292////////////////////////////////////////////////////////////////////
293//
294// Macro Memory-format instructions
295//
296
297def template MacroMemDeclare {{
298/**
299 * Static instructions class for a store multiple instruction
300 */
301class %(class_name)s : public %(base_class)s
302{
303 public:
304 // Constructor
305 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
306 bool index, bool up, bool user, bool writeback, bool load,
307 uint32_t reglist);
308 %(BasicExecPanic)s
309};
310}};
311
312def template MacroMemConstructor {{
313%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
314 bool index, bool up, bool user, bool writeback, bool load,
315 uint32_t reglist)
316 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
317 index, up, user, writeback, load, reglist)
318{
319 %(constructor)s;
| 329 }
330}};
331
332////////////////////////////////////////////////////////////////////
333//
334// Macro Memory-format instructions
335//
336
337def template MacroMemDeclare {{
338/**
339 * Static instructions class for a store multiple instruction
340 */
341class %(class_name)s : public %(base_class)s
342{
343 public:
344 // Constructor
345 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
346 bool index, bool up, bool user, bool writeback, bool load,
347 uint32_t reglist);
348 %(BasicExecPanic)s
349};
350}};
351
352def template MacroMemConstructor {{
353%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
354 bool index, bool up, bool user, bool writeback, bool load,
355 uint32_t reglist)
356 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
357 index, up, user, writeback, load, reglist)
358{
359 %(constructor)s;
|
| 360 if (!(condCode == COND_AL || condCode == COND_UC)) {
361 for (int x = 0; x < _numDestRegs; x++) {
362 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
363 }
364 }
|
320}
321
322}};
323
324def template VMemMultDeclare {{
325class %(class_name)s : public %(base_class)s
326{
327 public:
328 // Constructor
329 %(class_name)s(ExtMachInst machInst, unsigned width,
330 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
331 uint32_t size, uint32_t align, RegIndex rm);
332 %(BasicExecPanic)s
333};
334}};
335
336def template VMemMultConstructor {{
337%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
338 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
339 uint32_t size, uint32_t align, RegIndex rm)
340 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
341 rn, vd, regs, inc, size, align, rm)
342{
343 %(constructor)s;
| 365}
366
367}};
368
369def template VMemMultDeclare {{
370class %(class_name)s : public %(base_class)s
371{
372 public:
373 // Constructor
374 %(class_name)s(ExtMachInst machInst, unsigned width,
375 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
376 uint32_t size, uint32_t align, RegIndex rm);
377 %(BasicExecPanic)s
378};
379}};
380
381def template VMemMultConstructor {{
382%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
383 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
384 uint32_t size, uint32_t align, RegIndex rm)
385 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
386 rn, vd, regs, inc, size, align, rm)
387{
388 %(constructor)s;
|
| 389 if (!(condCode == COND_AL || condCode == COND_UC)) {
390 for (int x = 0; x < _numDestRegs; x++) {
391 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
392 }
393 }
|
344}
345}};
346
347def template VMemSingleDeclare {{
348class %(class_name)s : public %(base_class)s
349{
350 public:
351 // Constructor
352 %(class_name)s(ExtMachInst machInst, bool all, unsigned width,
353 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
354 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
355 %(BasicExecPanic)s
356};
357}};
358
359def template VMemSingleConstructor {{
360%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
361 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
362 uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
363 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
364 rn, vd, regs, inc, size, align, rm, lane)
365{
366 %(constructor)s;
| 394}
395}};
396
397def template VMemSingleDeclare {{
398class %(class_name)s : public %(base_class)s
399{
400 public:
401 // Constructor
402 %(class_name)s(ExtMachInst machInst, bool all, unsigned width,
403 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
404 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
405 %(BasicExecPanic)s
406};
407}};
408
409def template VMemSingleConstructor {{
410%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
411 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
412 uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
413 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
414 rn, vd, regs, inc, size, align, rm, lane)
415{
416 %(constructor)s;
|
| 417 if (!(condCode == COND_AL || condCode == COND_UC)) {
418 for (int x = 0; x < _numDestRegs; x++) {
419 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
420 }
421 }
|
367}
368}};
369
370def template MacroVFPMemDeclare {{
371/**
372 * Static instructions class for a store multiple instruction
373 */
374class %(class_name)s : public %(base_class)s
375{
376 public:
377 // Constructor
378 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
379 RegIndex vd, bool single, bool up, bool writeback,
380 bool load, uint32_t offset);
381 %(BasicExecPanic)s
382};
383}};
384
385def template MacroVFPMemConstructor {{
386%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
387 RegIndex vd, bool single, bool up, bool writeback, bool load,
388 uint32_t offset)
389 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
390 vd, single, up, writeback, load, offset)
391{
392 %(constructor)s;
| 422}
423}};
424
425def template MacroVFPMemDeclare {{
426/**
427 * Static instructions class for a store multiple instruction
428 */
429class %(class_name)s : public %(base_class)s
430{
431 public:
432 // Constructor
433 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
434 RegIndex vd, bool single, bool up, bool writeback,
435 bool load, uint32_t offset);
436 %(BasicExecPanic)s
437};
438}};
439
440def template MacroVFPMemConstructor {{
441%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
442 RegIndex vd, bool single, bool up, bool writeback, bool load,
443 uint32_t offset)
444 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
445 vd, single, up, writeback, load, offset)
446{
447 %(constructor)s;
|
| 448 if (!(condCode == COND_AL || condCode == COND_UC)) {
449 for (int x = 0; x < _numDestRegs; x++) {
450 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
451 }
452 }
|
393}
394
395}};
| 453}
454
455}};
|