80//////////////////////////////////////////////////////////////////// 81// 82// Neon load/store microops 83// 84 85def template MicroNeonMemDeclare {{ 86 template <class Element> 87 class %(class_name)s : public %(base_class)s 88 { 89 public: 90 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 92 : %(base_class)s("%(mnemonic)s", machInst, 93 %(op_class)s, _dest, _ura, _imm) 94 { 95 memAccessFlags |= extraMemFlags; 96 %(constructor)s; 97 if (!(condCode == COND_AL || condCode == COND_UC)) { 98 for (int x = 0; x < _numDestRegs; x++) { 99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 100 } 101 } 102 } 103 104 %(BasicExecDeclare)s 105 %(InitiateAccDeclare)s 106 %(CompleteAccDeclare)s 107 }; 108}}; 109 110//////////////////////////////////////////////////////////////////// 111// 112// PC = Integer(ura) 113// CPSR = Integer(urb) 114// 115 116def template MicroSetPCCPSRDeclare {{ 117 class %(class_name)s : public %(base_class)s 118 { 119 public: 120 %(class_name)s(ExtMachInst machInst, 121 IntRegIndex _ura, 122 IntRegIndex _urb, 123 IntRegIndex _urc); 124 %(BasicExecDeclare)s 125 }; 126}}; 127 128def template MicroSetPCCPSRConstructor {{ 129 %(class_name)s::%(class_name)s(ExtMachInst machInst, 130 IntRegIndex _ura, 131 IntRegIndex _urb, 132 IntRegIndex _urc) 133 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 134 _ura, _urb, _urc) 135 { 136 %(constructor)s; 137 if (!(condCode == COND_AL || condCode == COND_UC)) { 138 flags[IsCondControl] = true; 139 for (int x = 0; x < _numDestRegs; x++) { 140 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 141 } 142 } else { 143 flags[IsUncondControl] = true; 144 } 145 } 146}}; 147 148//////////////////////////////////////////////////////////////////// 149// 150// Integer = Integer op Integer microops 151// 152 153def template MicroIntDeclare {{ 154 class %(class_name)s : public %(base_class)s 155 { 156 public: 157 %(class_name)s(ExtMachInst machInst, 158 RegIndex _ura, RegIndex _urb, RegIndex _urc); 159 %(BasicExecDeclare)s 160 }; 161}}; 162 163def template MicroIntConstructor {{ 164 %(class_name)s::%(class_name)s(ExtMachInst machInst, 165 RegIndex _ura, 166 RegIndex _urb, 167 RegIndex _urc) 168 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 169 _ura, _urb, _urc) 170 { 171 %(constructor)s; 172 if (!(condCode == COND_AL || condCode == COND_UC)) { 173 for (int x = 0; x < _numDestRegs; x++) { 174 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 175 } 176 } 177 } 178}}; 179 180def template MicroNeonMemExecDeclare {{ 181 template 182 Fault %(class_name)s<%(targs)s>::execute( 183 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 184 template 185 Fault %(class_name)s<%(targs)s>::initiateAcc( 186 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 187 template 188 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 189 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 190}}; 191 192def template MicroNeonExecDeclare {{ 193 template 194 Fault %(class_name)s<%(targs)s>::execute( 195 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 196}}; 197 198//////////////////////////////////////////////////////////////////// 199// 200// Neon (de)interlacing microops 201// 202 203def template MicroNeonMixDeclare {{ 204 template <class Element> 205 class %(class_name)s : public %(base_class)s 206 { 207 public: 208 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 209 uint8_t _step) : 210 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 211 _dest, _op1, _step) 212 { 213 %(constructor)s; 214 if (!(condCode == COND_AL || condCode == COND_UC)) { 215 for (int x = 0; x < _numDestRegs; x++) { 216 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 217 } 218 } 219 } 220 221 %(BasicExecDeclare)s 222 }; 223}}; 224 225def template MicroNeonMixExecute {{ 226 template <class Element> 227 Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, 228 Trace::InstRecord *traceData) const 229 { 230 Fault fault = NoFault; 231 uint64_t resTemp = 0; 232 resTemp = resTemp; 233 %(op_decl)s; 234 %(op_rd)s; 235 236 if (%(predicate_test)s) 237 { 238 %(code)s; 239 if (fault == NoFault) 240 { 241 %(op_wb)s; 242 } 243 } else { 244 xc->setPredicate(false); 245 } 246 247 return fault; 248 } 249}}; 250 251//////////////////////////////////////////////////////////////////// 252// 253// Neon (un)packing microops using a particular lane 254// 255 256def template MicroNeonMixLaneDeclare {{ 257 template <class Element> 258 class %(class_name)s : public %(base_class)s 259 { 260 public: 261 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 262 uint8_t _step, unsigned _lane) : 263 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 264 _dest, _op1, _step, _lane) 265 { 266 %(constructor)s; 267 if (!(condCode == COND_AL || condCode == COND_UC)) { 268 for (int x = 0; x < _numDestRegs; x++) { 269 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 270 } 271 } 272 } 273 274 %(BasicExecDeclare)s 275 }; 276}}; 277 278//////////////////////////////////////////////////////////////////// 279// 280// Integer = Integer 281// 282 283def template MicroIntMovDeclare {{ 284 class %(class_name)s : public %(base_class)s 285 { 286 public: 287 %(class_name)s(ExtMachInst machInst, 288 RegIndex _ura, RegIndex _urb); 289 %(BasicExecDeclare)s 290 }; 291}}; 292def template MicroIntMovConstructor {{ 293 %(class_name)s::%(class_name)s(ExtMachInst machInst, 294 RegIndex _ura, 295 RegIndex _urb) 296 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 297 _ura, _urb) 298 { 299 %(constructor)s; 300 if (!(condCode == COND_AL || condCode == COND_UC)) { 301 for (int x = 0; x < _numDestRegs; x++) { 302 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 303 } 304 } 305 } 306}}; 307 308//////////////////////////////////////////////////////////////////// 309// 310// Integer = Integer op Immediate microops 311// 312 313def template MicroIntImmDeclare {{ 314 class %(class_name)s : public %(base_class)s 315 { 316 public: 317 %(class_name)s(ExtMachInst machInst, 318 RegIndex _ura, RegIndex _urb, 319 int32_t _imm); 320 %(BasicExecDeclare)s 321 }; 322}}; 323 324def template MicroIntImmConstructor {{ 325 %(class_name)s::%(class_name)s(ExtMachInst machInst, 326 RegIndex _ura, 327 RegIndex _urb, 328 int32_t _imm) 329 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 330 _ura, _urb, _imm) 331 { 332 %(constructor)s; 333 if (!(condCode == COND_AL || condCode == COND_UC)) { 334 for (int x = 0; x < _numDestRegs; x++) { 335 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 336 } 337 } 338 } 339}}; 340 341def template MicroIntImmXConstructor {{ 342 %(class_name)s::%(class_name)s(ExtMachInst machInst, 343 RegIndex _ura, 344 RegIndex _urb, 345 int32_t _imm) 346 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 347 _ura, _urb, _imm) 348 { 349 %(constructor)s; 350 } 351}}; 352 353def template MicroIntRegDeclare {{ 354 class %(class_name)s : public %(base_class)s 355 { 356 public: 357 %(class_name)s(ExtMachInst machInst, 358 RegIndex _ura, RegIndex _urb, RegIndex _urc, 359 int32_t _shiftAmt, ArmShiftType _shiftType); 360 %(BasicExecDeclare)s 361 }; 362}}; 363 364def template MicroIntXERegConstructor {{ 365 %(class_name)s::%(class_name)s(ExtMachInst machInst, 366 RegIndex _ura, RegIndex _urb, RegIndex _urc, 367 ArmExtendType _type, uint32_t _shiftAmt) 368 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 369 _ura, _urb, _urc, _type, _shiftAmt) 370 { 371 %(constructor)s; 372 } 373}}; 374 375def template MicroIntXERegDeclare {{ 376 class %(class_name)s : public %(base_class)s 377 { 378 public: 379 %(class_name)s(ExtMachInst machInst, 380 RegIndex _ura, RegIndex _urb, RegIndex _urc, 381 ArmExtendType _type, uint32_t _shiftAmt); 382 %(BasicExecDeclare)s 383 }; 384}}; 385 386def template MicroIntRegConstructor {{ 387 %(class_name)s::%(class_name)s(ExtMachInst machInst, 388 RegIndex _ura, RegIndex _urb, RegIndex _urc, 389 int32_t _shiftAmt, ArmShiftType _shiftType) 390 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 391 _ura, _urb, _urc, _shiftAmt, _shiftType) 392 { 393 %(constructor)s; 394 if (!(condCode == COND_AL || condCode == COND_UC)) { 395 for (int x = 0; x < _numDestRegs; x++) { 396 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 397 } 398 } 399 } 400}}; 401 402//////////////////////////////////////////////////////////////////// 403// 404// Macro Memory-format instructions 405// 406 407def template MacroMemDeclare {{ 408/** 409 * Static instructions class for a store multiple instruction 410 */ 411class %(class_name)s : public %(base_class)s 412{ 413 public: 414 // Constructor 415 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 416 bool index, bool up, bool user, bool writeback, bool load, 417 uint32_t reglist); 418 %(BasicExecPanic)s 419}; 420}}; 421 422def template MacroMemConstructor {{ 423%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 424 bool index, bool up, bool user, bool writeback, bool load, 425 uint32_t reglist) 426 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 427 index, up, user, writeback, load, reglist) 428{ 429 %(constructor)s; 430 if (!(condCode == COND_AL || condCode == COND_UC)) { 431 for (int x = 0; x < _numDestRegs; x++) { 432 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 433 } 434 } 435} 436 437}}; 438 439def template BigFpMemImmDeclare {{ 440class %(class_name)s : public %(base_class)s 441{ 442 public: 443 // Constructor 444 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 445 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 446 %(BasicExecPanic)s 447}; 448}}; 449 450def template BigFpMemImmConstructor {{ 451%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 452 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 453 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 454{ 455 %(constructor)s; 456} 457}}; 458 459def template BigFpMemRegDeclare {{ 460class %(class_name)s : public %(base_class)s 461{ 462 public: 463 // Constructor 464 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 465 bool load, IntRegIndex dest, IntRegIndex base, 466 IntRegIndex offset, ArmExtendType type, int64_t imm); 467 %(BasicExecPanic)s 468}; 469}}; 470 471def template BigFpMemRegConstructor {{ 472%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 473 bool load, IntRegIndex dest, IntRegIndex base, 474 IntRegIndex offset, ArmExtendType type, int64_t imm) 475 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 476 offset, type, imm) 477{ 478 %(constructor)s; 479} 480}}; 481 482def template BigFpMemLitDeclare {{ 483class %(class_name)s : public %(base_class)s 484{ 485 public: 486 // Constructor 487 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 488 IntRegIndex dest, int64_t imm); 489 %(BasicExecPanic)s 490}; 491}}; 492 493def template BigFpMemLitConstructor {{ 494%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 495 IntRegIndex dest, int64_t imm) 496 : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 497{ 498 %(constructor)s; 499} 500}}; 501 502def template PairMemDeclare {{ 503class %(class_name)s : public %(base_class)s 504{ 505 public: 506 // Constructor 507 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 508 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 509 bool exclusive, bool acrel, uint32_t imm, 510 AddrMode mode, IntRegIndex rn, IntRegIndex rt, 511 IntRegIndex rt2); 512 %(BasicExecPanic)s 513}; 514}}; 515 516def template PairMemConstructor {{ 517%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 518 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 519 bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 520 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 521 : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 522 fp, load, noAlloc, signExt, exclusive, acrel, 523 imm, mode, rn, rt, rt2) 524{ 525 %(constructor)s; 526} 527}}; 528 529def template VMemMultDeclare {{ 530class %(class_name)s : public %(base_class)s 531{ 532 public: 533 // Constructor 534 %(class_name)s(ExtMachInst machInst, unsigned width, 535 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 536 uint32_t size, uint32_t align, RegIndex rm); 537 %(BasicExecPanic)s 538}; 539}}; 540 541def template VMemMultConstructor {{ 542%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 543 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 544 uint32_t size, uint32_t align, RegIndex rm) 545 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 546 rn, vd, regs, inc, size, align, rm) 547{ 548 %(constructor)s; 549 if (!(condCode == COND_AL || condCode == COND_UC)) { 550 for (int x = 0; x < _numDestRegs; x++) { 551 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 552 } 553 } 554} 555}}; 556 557def template VMemSingleDeclare {{ 558class %(class_name)s : public %(base_class)s 559{ 560 public: 561 // Constructor 562 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 563 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 564 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 565 %(BasicExecPanic)s 566}; 567}}; 568 569def template VMemSingleConstructor {{ 570%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 571 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 572 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 573 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 574 rn, vd, regs, inc, size, align, rm, lane) 575{ 576 %(constructor)s; 577 if (!(condCode == COND_AL || condCode == COND_UC)) { 578 for (int x = 0; x < _numDestRegs; x++) { 579 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 580 } 581 } 582} 583}}; 584 585def template MacroVFPMemDeclare {{ 586/** 587 * Static instructions class for a store multiple instruction 588 */ 589class %(class_name)s : public %(base_class)s 590{ 591 public: 592 // Constructor 593 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 594 RegIndex vd, bool single, bool up, bool writeback, 595 bool load, uint32_t offset); 596 %(BasicExecPanic)s 597}; 598}}; 599 600def template MacroVFPMemConstructor {{ 601%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 602 RegIndex vd, bool single, bool up, bool writeback, bool load, 603 uint32_t offset) 604 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 605 vd, single, up, writeback, load, offset) 606{ 607 %(constructor)s; 608 if (!(condCode == COND_AL || condCode == COND_UC)) { 609 for (int x = 0; x < _numDestRegs; x++) { 610 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 611 } 612 } 613} 614 615}};
| 113//////////////////////////////////////////////////////////////////// 114// 115// Neon load/store microops 116// 117 118def template MicroNeonMemDeclare {{ 119 template <class Element> 120 class %(class_name)s : public %(base_class)s 121 { 122 public: 123 %(class_name)s(ExtMachInst machInst, RegIndex _dest, 124 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 125 : %(base_class)s("%(mnemonic)s", machInst, 126 %(op_class)s, _dest, _ura, _imm) 127 { 128 memAccessFlags |= extraMemFlags; 129 %(constructor)s; 130 if (!(condCode == COND_AL || condCode == COND_UC)) { 131 for (int x = 0; x < _numDestRegs; x++) { 132 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 133 } 134 } 135 } 136 137 %(BasicExecDeclare)s 138 %(InitiateAccDeclare)s 139 %(CompleteAccDeclare)s 140 }; 141}}; 142 143//////////////////////////////////////////////////////////////////// 144// 145// PC = Integer(ura) 146// CPSR = Integer(urb) 147// 148 149def template MicroSetPCCPSRDeclare {{ 150 class %(class_name)s : public %(base_class)s 151 { 152 public: 153 %(class_name)s(ExtMachInst machInst, 154 IntRegIndex _ura, 155 IntRegIndex _urb, 156 IntRegIndex _urc); 157 %(BasicExecDeclare)s 158 }; 159}}; 160 161def template MicroSetPCCPSRConstructor {{ 162 %(class_name)s::%(class_name)s(ExtMachInst machInst, 163 IntRegIndex _ura, 164 IntRegIndex _urb, 165 IntRegIndex _urc) 166 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 167 _ura, _urb, _urc) 168 { 169 %(constructor)s; 170 if (!(condCode == COND_AL || condCode == COND_UC)) { 171 flags[IsCondControl] = true; 172 for (int x = 0; x < _numDestRegs; x++) { 173 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 174 } 175 } else { 176 flags[IsUncondControl] = true; 177 } 178 } 179}}; 180 181//////////////////////////////////////////////////////////////////// 182// 183// Integer = Integer op Integer microops 184// 185 186def template MicroIntDeclare {{ 187 class %(class_name)s : public %(base_class)s 188 { 189 public: 190 %(class_name)s(ExtMachInst machInst, 191 RegIndex _ura, RegIndex _urb, RegIndex _urc); 192 %(BasicExecDeclare)s 193 }; 194}}; 195 196def template MicroIntConstructor {{ 197 %(class_name)s::%(class_name)s(ExtMachInst machInst, 198 RegIndex _ura, 199 RegIndex _urb, 200 RegIndex _urc) 201 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 202 _ura, _urb, _urc) 203 { 204 %(constructor)s; 205 if (!(condCode == COND_AL || condCode == COND_UC)) { 206 for (int x = 0; x < _numDestRegs; x++) { 207 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 208 } 209 } 210 } 211}}; 212 213def template MicroNeonMemExecDeclare {{ 214 template 215 Fault %(class_name)s<%(targs)s>::execute( 216 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 217 template 218 Fault %(class_name)s<%(targs)s>::initiateAcc( 219 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 220 template 221 Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 222 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 223}}; 224 225def template MicroNeonExecDeclare {{ 226 template 227 Fault %(class_name)s<%(targs)s>::execute( 228 CPU_EXEC_CONTEXT *, Trace::InstRecord *) const; 229}}; 230 231//////////////////////////////////////////////////////////////////// 232// 233// Neon (de)interlacing microops 234// 235 236def template MicroNeonMixDeclare {{ 237 template <class Element> 238 class %(class_name)s : public %(base_class)s 239 { 240 public: 241 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 242 uint8_t _step) : 243 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 244 _dest, _op1, _step) 245 { 246 %(constructor)s; 247 if (!(condCode == COND_AL || condCode == COND_UC)) { 248 for (int x = 0; x < _numDestRegs; x++) { 249 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 250 } 251 } 252 } 253 254 %(BasicExecDeclare)s 255 }; 256}}; 257 258def template MicroNeonMixExecute {{ 259 template <class Element> 260 Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Fault fault = NoFault; 264 uint64_t resTemp = 0; 265 resTemp = resTemp; 266 %(op_decl)s; 267 %(op_rd)s; 268 269 if (%(predicate_test)s) 270 { 271 %(code)s; 272 if (fault == NoFault) 273 { 274 %(op_wb)s; 275 } 276 } else { 277 xc->setPredicate(false); 278 } 279 280 return fault; 281 } 282}}; 283 284//////////////////////////////////////////////////////////////////// 285// 286// Neon (un)packing microops using a particular lane 287// 288 289def template MicroNeonMixLaneDeclare {{ 290 template <class Element> 291 class %(class_name)s : public %(base_class)s 292 { 293 public: 294 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 295 uint8_t _step, unsigned _lane) : 296 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 297 _dest, _op1, _step, _lane) 298 { 299 %(constructor)s; 300 if (!(condCode == COND_AL || condCode == COND_UC)) { 301 for (int x = 0; x < _numDestRegs; x++) { 302 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 303 } 304 } 305 } 306 307 %(BasicExecDeclare)s 308 }; 309}}; 310 311//////////////////////////////////////////////////////////////////// 312// 313// Integer = Integer 314// 315 316def template MicroIntMovDeclare {{ 317 class %(class_name)s : public %(base_class)s 318 { 319 public: 320 %(class_name)s(ExtMachInst machInst, 321 RegIndex _ura, RegIndex _urb); 322 %(BasicExecDeclare)s 323 }; 324}}; 325def template MicroIntMovConstructor {{ 326 %(class_name)s::%(class_name)s(ExtMachInst machInst, 327 RegIndex _ura, 328 RegIndex _urb) 329 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 330 _ura, _urb) 331 { 332 %(constructor)s; 333 if (!(condCode == COND_AL || condCode == COND_UC)) { 334 for (int x = 0; x < _numDestRegs; x++) { 335 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 336 } 337 } 338 } 339}}; 340 341//////////////////////////////////////////////////////////////////// 342// 343// Integer = Integer op Immediate microops 344// 345 346def template MicroIntImmDeclare {{ 347 class %(class_name)s : public %(base_class)s 348 { 349 public: 350 %(class_name)s(ExtMachInst machInst, 351 RegIndex _ura, RegIndex _urb, 352 int32_t _imm); 353 %(BasicExecDeclare)s 354 }; 355}}; 356 357def template MicroIntImmConstructor {{ 358 %(class_name)s::%(class_name)s(ExtMachInst machInst, 359 RegIndex _ura, 360 RegIndex _urb, 361 int32_t _imm) 362 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 363 _ura, _urb, _imm) 364 { 365 %(constructor)s; 366 if (!(condCode == COND_AL || condCode == COND_UC)) { 367 for (int x = 0; x < _numDestRegs; x++) { 368 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 369 } 370 } 371 } 372}}; 373 374def template MicroIntImmXConstructor {{ 375 %(class_name)s::%(class_name)s(ExtMachInst machInst, 376 RegIndex _ura, 377 RegIndex _urb, 378 int32_t _imm) 379 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 380 _ura, _urb, _imm) 381 { 382 %(constructor)s; 383 } 384}}; 385 386def template MicroIntRegDeclare {{ 387 class %(class_name)s : public %(base_class)s 388 { 389 public: 390 %(class_name)s(ExtMachInst machInst, 391 RegIndex _ura, RegIndex _urb, RegIndex _urc, 392 int32_t _shiftAmt, ArmShiftType _shiftType); 393 %(BasicExecDeclare)s 394 }; 395}}; 396 397def template MicroIntXERegConstructor {{ 398 %(class_name)s::%(class_name)s(ExtMachInst machInst, 399 RegIndex _ura, RegIndex _urb, RegIndex _urc, 400 ArmExtendType _type, uint32_t _shiftAmt) 401 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 402 _ura, _urb, _urc, _type, _shiftAmt) 403 { 404 %(constructor)s; 405 } 406}}; 407 408def template MicroIntXERegDeclare {{ 409 class %(class_name)s : public %(base_class)s 410 { 411 public: 412 %(class_name)s(ExtMachInst machInst, 413 RegIndex _ura, RegIndex _urb, RegIndex _urc, 414 ArmExtendType _type, uint32_t _shiftAmt); 415 %(BasicExecDeclare)s 416 }; 417}}; 418 419def template MicroIntRegConstructor {{ 420 %(class_name)s::%(class_name)s(ExtMachInst machInst, 421 RegIndex _ura, RegIndex _urb, RegIndex _urc, 422 int32_t _shiftAmt, ArmShiftType _shiftType) 423 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 424 _ura, _urb, _urc, _shiftAmt, _shiftType) 425 { 426 %(constructor)s; 427 if (!(condCode == COND_AL || condCode == COND_UC)) { 428 for (int x = 0; x < _numDestRegs; x++) { 429 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 430 } 431 } 432 } 433}}; 434 435//////////////////////////////////////////////////////////////////// 436// 437// Macro Memory-format instructions 438// 439 440def template MacroMemDeclare {{ 441/** 442 * Static instructions class for a store multiple instruction 443 */ 444class %(class_name)s : public %(base_class)s 445{ 446 public: 447 // Constructor 448 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 449 bool index, bool up, bool user, bool writeback, bool load, 450 uint32_t reglist); 451 %(BasicExecPanic)s 452}; 453}}; 454 455def template MacroMemConstructor {{ 456%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 457 bool index, bool up, bool user, bool writeback, bool load, 458 uint32_t reglist) 459 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 460 index, up, user, writeback, load, reglist) 461{ 462 %(constructor)s; 463 if (!(condCode == COND_AL || condCode == COND_UC)) { 464 for (int x = 0; x < _numDestRegs; x++) { 465 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 466 } 467 } 468} 469 470}}; 471 472def template BigFpMemImmDeclare {{ 473class %(class_name)s : public %(base_class)s 474{ 475 public: 476 // Constructor 477 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 478 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); 479 %(BasicExecPanic)s 480}; 481}}; 482 483def template BigFpMemImmConstructor {{ 484%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 485 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) 486 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm) 487{ 488 %(constructor)s; 489} 490}}; 491 492def template BigFpMemRegDeclare {{ 493class %(class_name)s : public %(base_class)s 494{ 495 public: 496 // Constructor 497 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 498 bool load, IntRegIndex dest, IntRegIndex base, 499 IntRegIndex offset, ArmExtendType type, int64_t imm); 500 %(BasicExecPanic)s 501}; 502}}; 503 504def template BigFpMemRegConstructor {{ 505%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 506 bool load, IntRegIndex dest, IntRegIndex base, 507 IntRegIndex offset, ArmExtendType type, int64_t imm) 508 : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, 509 offset, type, imm) 510{ 511 %(constructor)s; 512} 513}}; 514 515def template BigFpMemLitDeclare {{ 516class %(class_name)s : public %(base_class)s 517{ 518 public: 519 // Constructor 520 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 521 IntRegIndex dest, int64_t imm); 522 %(BasicExecPanic)s 523}; 524}}; 525 526def template BigFpMemLitConstructor {{ 527%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 528 IntRegIndex dest, int64_t imm) 529 : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm) 530{ 531 %(constructor)s; 532} 533}}; 534 535def template PairMemDeclare {{ 536class %(class_name)s : public %(base_class)s 537{ 538 public: 539 // Constructor 540 %(class_name)s(const char *mnemonic, ExtMachInst machInst, 541 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 542 bool exclusive, bool acrel, uint32_t imm, 543 AddrMode mode, IntRegIndex rn, IntRegIndex rt, 544 IntRegIndex rt2); 545 %(BasicExecPanic)s 546}; 547}}; 548 549def template PairMemConstructor {{ 550%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst, 551 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, 552 bool exclusive, bool acrel, uint32_t imm, AddrMode mode, 553 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) 554 : %(base_class)s(mnemonic, machInst, %(op_class)s, size, 555 fp, load, noAlloc, signExt, exclusive, acrel, 556 imm, mode, rn, rt, rt2) 557{ 558 %(constructor)s; 559} 560}}; 561 562def template VMemMultDeclare {{ 563class %(class_name)s : public %(base_class)s 564{ 565 public: 566 // Constructor 567 %(class_name)s(ExtMachInst machInst, unsigned width, 568 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 569 uint32_t size, uint32_t align, RegIndex rm); 570 %(BasicExecPanic)s 571}; 572}}; 573 574def template VMemMultConstructor {{ 575%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 576 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 577 uint32_t size, uint32_t align, RegIndex rm) 578 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 579 rn, vd, regs, inc, size, align, rm) 580{ 581 %(constructor)s; 582 if (!(condCode == COND_AL || condCode == COND_UC)) { 583 for (int x = 0; x < _numDestRegs; x++) { 584 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 585 } 586 } 587} 588}}; 589 590def template VMemSingleDeclare {{ 591class %(class_name)s : public %(base_class)s 592{ 593 public: 594 // Constructor 595 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 596 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 597 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 598 %(BasicExecPanic)s 599}; 600}}; 601 602def template VMemSingleConstructor {{ 603%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 604 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 605 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 606 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 607 rn, vd, regs, inc, size, align, rm, lane) 608{ 609 %(constructor)s; 610 if (!(condCode == COND_AL || condCode == COND_UC)) { 611 for (int x = 0; x < _numDestRegs; x++) { 612 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 613 } 614 } 615} 616}}; 617 618def template MacroVFPMemDeclare {{ 619/** 620 * Static instructions class for a store multiple instruction 621 */ 622class %(class_name)s : public %(base_class)s 623{ 624 public: 625 // Constructor 626 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 627 RegIndex vd, bool single, bool up, bool writeback, 628 bool load, uint32_t offset); 629 %(BasicExecPanic)s 630}; 631}}; 632 633def template MacroVFPMemConstructor {{ 634%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 635 RegIndex vd, bool single, bool up, bool writeback, bool load, 636 uint32_t offset) 637 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 638 vd, single, up, writeback, load, offset) 639{ 640 %(constructor)s; 641 if (!(condCode == COND_AL || condCode == COND_UC)) { 642 for (int x = 0; x < _numDestRegs; x++) { 643 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 644 } 645 } 646} 647 648}};
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