1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder. You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42// Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49def template MicroMemDeclare {{
50 class %(class_name)s : public %(base_class)s
51 {
52 public:
53 %(class_name)s(ExtMachInst machInst,
54 RegIndex _ura, RegIndex _urb, bool _up,
55 uint8_t _imm);
56 %(BasicExecDeclare)s
57 %(InitiateAccDeclare)s
58 %(CompleteAccDeclare)s
59 };
60}};
61
62def template MicroMemConstructor {{
63 %(class_name)s::%(class_name)s(ExtMachInst machInst,
64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,
67 uint8_t _imm)
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69 _ura, _urb, _up, _imm)
70 {
71 %(constructor)s;
72 }
73}};
74
75////////////////////////////////////////////////////////////////////
76//
77// Integer = Integer op Immediate microops
78//
79
80def template MicroIntDeclare {{
81 class %(class_name)s : public %(base_class)s
82 {
83 public:
84 %(class_name)s(ExtMachInst machInst,
85 RegIndex _ura, RegIndex _urb,
86 uint8_t _imm);
87 %(BasicExecDeclare)s
88 };
89}};
90
91def template MicroIntConstructor {{
92 %(class_name)s::%(class_name)s(ExtMachInst machInst,
93 RegIndex _ura,
94 RegIndex _urb,
95 uint8_t _imm)
96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
97 _ura, _urb, _imm)
98 {
99 %(constructor)s;
100 }
101}};
102
103////////////////////////////////////////////////////////////////////
104//
105// Macro Memory-format instructions
106//
107
108def template MacroMemDeclare {{
109/**
110 * Static instructions class for a store multiple instruction
111 */
112class %(class_name)s : public %(base_class)s
113{
114 public:
115 // Constructor
116 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
117 bool index, bool up, bool user, bool writeback, bool load,
118 uint32_t reglist);
119 %(BasicExecPanic)s
120};
121}};
122
123def template MacroMemConstructor {{
124%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
125 bool index, bool up, bool user, bool writeback, bool load,
126 uint32_t reglist)
127 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
128 index, up, user, writeback, load, reglist)
129{
130 %(constructor)s;
131}
132
133}};
134
135def template MacroVFPMemDeclare {{
136/**
137 * Static instructions class for a store multiple instruction
138 */
139class %(class_name)s : public %(base_class)s
140{
141 public:
142 // Constructor
143 %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
144 RegIndex vd, bool single, bool up, bool writeback,
145 bool load, uint32_t offset);
146 %(BasicExecPanic)s
147};
148}};
149
150def template MacroVFPMemConstructor {{
151%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
152 RegIndex vd, bool single, bool up, bool writeback, bool load,
153 uint32_t offset)
154 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
155 vd, single, up, writeback, load, offset)
156{
157 %(constructor)s;
158}
159
160}};