1// -*- mode:c++ -*-
2
3// Copyright (c) 2010-2014 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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48
49def template MicroMemDeclare {{
50 class %(class_name)s : public %(base_class)s
51 {
52 public:
53 %(class_name)s(ExtMachInst machInst,
54 RegIndex _ura, RegIndex _urb, bool _up,
55 uint8_t _imm);
56 Fault execute(ExecContext *, Trace::InstRecord *) const;
57 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
58 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
59 };
60}};
61
62def template MicroMemConstructor {{
63 %(class_name)s::%(class_name)s(ExtMachInst machInst,
64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,

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80
81def template MicroMemPairDeclare {{
82 class %(class_name)s : public %(base_class)s
83 {
84 public:
85 %(class_name)s(ExtMachInst machInst,
86 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
87 bool _up, uint8_t _imm);
88 Fault execute(ExecContext *, Trace::InstRecord *) const;
89 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
90 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
91 };
92}};
93
94def template MicroMemPairConstructor {{
95 %(class_name)s::%(class_name)s(ExtMachInst machInst,
96 RegIndex _dreg1,
97 RegIndex _dreg2,
98 RegIndex _base,

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129 %(constructor)s;
130 if (!(condCode == COND_AL || condCode == COND_UC)) {
131 for (int x = 0; x < _numDestRegs; x++) {
132 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
133 }
134 }
135 }
136
137 Fault execute(ExecContext *, Trace::InstRecord *) const;
138 Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
139 Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
140 };
141}};
142
143////////////////////////////////////////////////////////////////////
144//
145// PC = Integer(ura)
146// CPSR = Integer(urb)
147//
148
149def template MicroSetPCCPSRDeclare {{
150 class %(class_name)s : public %(base_class)s
151 {
152 public:
153 %(class_name)s(ExtMachInst machInst,
154 IntRegIndex _ura,
155 IntRegIndex _urb,
156 IntRegIndex _urc);
157 Fault execute(ExecContext *, Trace::InstRecord *) const;
158 };
159}};
160
161def template MicroSetPCCPSRConstructor {{
162 %(class_name)s::%(class_name)s(ExtMachInst machInst,
163 IntRegIndex _ura,
164 IntRegIndex _urb,
165 IntRegIndex _urc)

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184//
185
186def template MicroIntDeclare {{
187 class %(class_name)s : public %(base_class)s
188 {
189 public:
190 %(class_name)s(ExtMachInst machInst,
191 RegIndex _ura, RegIndex _urb, RegIndex _urc);
192 Fault execute(ExecContext *, Trace::InstRecord *) const;
193 };
194}};
195
196def template MicroIntConstructor {{
197 %(class_name)s::%(class_name)s(ExtMachInst machInst,
198 RegIndex _ura,
199 RegIndex _urb,
200 RegIndex _urc)

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246 %(constructor)s;
247 if (!(condCode == COND_AL || condCode == COND_UC)) {
248 for (int x = 0; x < _numDestRegs; x++) {
249 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
250 }
251 }
252 }
253
254 Fault execute(ExecContext *, Trace::InstRecord *) const;
255 };
256}};
257
258def template MicroNeonMixExecute {{
259 template <class Element>
260 Fault %(class_name)s<Element>::execute(ExecContext *xc,
261 Trace::InstRecord *traceData) const
262 {

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299 %(constructor)s;
300 if (!(condCode == COND_AL || condCode == COND_UC)) {
301 for (int x = 0; x < _numDestRegs; x++) {
302 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
303 }
304 }
305 }
306
307 Fault execute(ExecContext *, Trace::InstRecord *) const;
308 };
309}};
310
311////////////////////////////////////////////////////////////////////
312//
313// Integer = Integer
314//
315
316def template MicroIntMovDeclare {{
317 class %(class_name)s : public %(base_class)s
318 {
319 public:
320 %(class_name)s(ExtMachInst machInst,
321 RegIndex _ura, RegIndex _urb);
322 Fault execute(ExecContext *, Trace::InstRecord *) const;
323 };
324}};
325def template MicroIntMovConstructor {{
326 %(class_name)s::%(class_name)s(ExtMachInst machInst,
327 RegIndex _ura,
328 RegIndex _urb)
329 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
330 _ura, _urb)

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345
346def template MicroIntImmDeclare {{
347 class %(class_name)s : public %(base_class)s
348 {
349 public:
350 %(class_name)s(ExtMachInst machInst,
351 RegIndex _ura, RegIndex _urb,
352 int32_t _imm);
353 Fault execute(ExecContext *, Trace::InstRecord *) const;
354 };
355}};
356
357def template MicroIntImmConstructor {{
358 %(class_name)s::%(class_name)s(ExtMachInst machInst,
359 RegIndex _ura,
360 RegIndex _urb,
361 int32_t _imm)

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385
386def template MicroIntRegDeclare {{
387 class %(class_name)s : public %(base_class)s
388 {
389 public:
390 %(class_name)s(ExtMachInst machInst,
391 RegIndex _ura, RegIndex _urb, RegIndex _urc,
392 int32_t _shiftAmt, ArmShiftType _shiftType);
393 Fault execute(ExecContext *, Trace::InstRecord *) const;
394 };
395}};
396
397def template MicroIntXERegConstructor {{
398 %(class_name)s::%(class_name)s(ExtMachInst machInst,
399 RegIndex _ura, RegIndex _urb, RegIndex _urc,
400 ArmExtendType _type, uint32_t _shiftAmt)
401 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,

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407
408def template MicroIntXERegDeclare {{
409 class %(class_name)s : public %(base_class)s
410 {
411 public:
412 %(class_name)s(ExtMachInst machInst,
413 RegIndex _ura, RegIndex _urb, RegIndex _urc,
414 ArmExtendType _type, uint32_t _shiftAmt);
415 Fault execute(ExecContext *, Trace::InstRecord *) const;
416 };
417}};
418
419def template MicroIntRegConstructor {{
420 %(class_name)s::%(class_name)s(ExtMachInst machInst,
421 RegIndex _ura, RegIndex _urb, RegIndex _urc,
422 int32_t _shiftAmt, ArmShiftType _shiftType)
423 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,

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