1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating

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64 RegIndex _ura,
65 RegIndex _urb,
66 bool _up,
67 uint8_t _imm)
68 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69 _ura, _urb, _up, _imm)
70 {
71 %(constructor)s;
72 if (!(condCode == COND_AL || condCode == COND_UC)) {
73 for (int x = 0; x < _numDestRegs; x++) {
74 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
75 }
76 }
77 }
78}};
79
80////////////////////////////////////////////////////////////////////
81//
82// Neon load/store microops
83//
84

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89 public:
90 %(class_name)s(ExtMachInst machInst, RegIndex _dest,
91 RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
92 : %(base_class)s("%(mnemonic)s", machInst,
93 %(op_class)s, _dest, _ura, _imm)
94 {
95 memAccessFlags |= extraMemFlags;
96 %(constructor)s;
97 if (!(condCode == COND_AL || condCode == COND_UC)) {
98 for (int x = 0; x < _numDestRegs; x++) {
99 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
100 }
101 }
102 }
103
104 %(BasicExecDeclare)s
105 %(InitiateAccDeclare)s
106 %(CompleteAccDeclare)s
107 };
108}};
109

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126 %(class_name)s::%(class_name)s(ExtMachInst machInst,
127 RegIndex _ura,
128 RegIndex _urb,
129 RegIndex _urc)
130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
131 _ura, _urb, _urc)
132 {
133 %(constructor)s;
134 if (!(condCode == COND_AL || condCode == COND_UC)) {
135 for (int x = 0; x < _numDestRegs; x++) {
136 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
137 }
138 }
139 }
140}};
141
142def template MicroNeonMemExecDeclare {{
143 template
144 Fault %(class_name)s<%(targs)s>::execute(
145 %(CPU_exec_context)s *, Trace::InstRecord *) const;
146 template

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168 {
169 public:
170 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
171 uint8_t _step) :
172 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
173 _dest, _op1, _step)
174 {
175 %(constructor)s;
176 if (!(condCode == COND_AL || condCode == COND_UC)) {
177 for (int x = 0; x < _numDestRegs; x++) {
178 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
179 }
180 }
181 }
182
183 %(BasicExecDeclare)s
184 };
185}};
186
187def template MicroNeonMixExecute {{
188 template <class Element>

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223 {
224 public:
225 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
226 uint8_t _step, unsigned _lane) :
227 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
228 _dest, _op1, _step, _lane)
229 {
230 %(constructor)s;
231 if (!(condCode == COND_AL || condCode == COND_UC)) {
232 for (int x = 0; x < _numDestRegs; x++) {
233 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
234 }
235 }
236 }
237
238 %(BasicExecDeclare)s
239 };
240}};
241
242////////////////////////////////////////////////////////////////////
243//

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256def template MicroIntMovConstructor {{
257 %(class_name)s::%(class_name)s(ExtMachInst machInst,
258 RegIndex _ura,
259 RegIndex _urb)
260 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
261 _ura, _urb)
262 {
263 %(constructor)s;
264 if (!(condCode == COND_AL || condCode == COND_UC)) {
265 for (int x = 0; x < _numDestRegs; x++) {
266 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
267 }
268 }
269 }
270}};
271
272////////////////////////////////////////////////////////////////////
273//
274// Integer = Integer op Immediate microops
275//
276

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289 %(class_name)s::%(class_name)s(ExtMachInst machInst,
290 RegIndex _ura,
291 RegIndex _urb,
292 int32_t _imm)
293 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
294 _ura, _urb, _imm)
295 {
296 %(constructor)s;
297 if (!(condCode == COND_AL || condCode == COND_UC)) {
298 for (int x = 0; x < _numDestRegs; x++) {
299 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
300 }
301 }
302 }
303}};
304
305def template MicroIntRegDeclare {{
306 class %(class_name)s : public %(base_class)s
307 {
308 public:
309 %(class_name)s(ExtMachInst machInst,

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316def template MicroIntRegConstructor {{
317 %(class_name)s::%(class_name)s(ExtMachInst machInst,
318 RegIndex _ura, RegIndex _urb, RegIndex _urc,
319 int32_t _shiftAmt, ArmShiftType _shiftType)
320 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
321 _ura, _urb, _urc, _shiftAmt, _shiftType)
322 {
323 %(constructor)s;
324 if (!(condCode == COND_AL || condCode == COND_UC)) {
325 for (int x = 0; x < _numDestRegs; x++) {
326 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
327 }
328 }
329 }
330}};
331
332////////////////////////////////////////////////////////////////////
333//
334// Macro Memory-format instructions
335//
336

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352def template MacroMemConstructor {{
353%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
354 bool index, bool up, bool user, bool writeback, bool load,
355 uint32_t reglist)
356 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
357 index, up, user, writeback, load, reglist)
358{
359 %(constructor)s;
360 if (!(condCode == COND_AL || condCode == COND_UC)) {
361 for (int x = 0; x < _numDestRegs; x++) {
362 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
363 }
364 }
365}
366
367}};
368
369def template VMemMultDeclare {{
370class %(class_name)s : public %(base_class)s
371{
372 public:

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381def template VMemMultConstructor {{
382%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
383 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
384 uint32_t size, uint32_t align, RegIndex rm)
385 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
386 rn, vd, regs, inc, size, align, rm)
387{
388 %(constructor)s;
389 if (!(condCode == COND_AL || condCode == COND_UC)) {
390 for (int x = 0; x < _numDestRegs; x++) {
391 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
392 }
393 }
394}
395}};
396
397def template VMemSingleDeclare {{
398class %(class_name)s : public %(base_class)s
399{
400 public:
401 // Constructor

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409def template VMemSingleConstructor {{
410%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
411 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
412 uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
413 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
414 rn, vd, regs, inc, size, align, rm, lane)
415{
416 %(constructor)s;
417 if (!(condCode == COND_AL || condCode == COND_UC)) {
418 for (int x = 0; x < _numDestRegs; x++) {
419 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
420 }
421 }
422}
423}};
424
425def template MacroVFPMemDeclare {{
426/**
427 * Static instructions class for a store multiple instruction
428 */
429class %(class_name)s : public %(base_class)s

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440def template MacroVFPMemConstructor {{
441%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
442 RegIndex vd, bool single, bool up, bool writeback, bool load,
443 uint32_t offset)
444 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
445 vd, single, up, writeback, load, offset)
446{
447 %(constructor)s;
448 if (!(condCode == COND_AL || condCode == COND_UC)) {
449 for (int x = 0; x < _numDestRegs; x++) {
450 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
451 }
452 }
453}
454
455}};