branch.isa (8203:78b9f056d58a) | branch.isa (8892:02b0b6b4d7c0) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 198 unchanged lines hidden (view full) --- 207 public: 208 // Constructor 209 %(class_name)s(ExtMachInst machInst, 210 int32_t imm, IntRegIndex _op1); 211 %(BasicExecDeclare)s 212}; 213}}; 214 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 198 unchanged lines hidden (view full) --- 207 public: 208 // Constructor 209 %(class_name)s(ExtMachInst machInst, 210 int32_t imm, IntRegIndex _op1); 211 %(BasicExecDeclare)s 212}; 213}}; 214 |
215// Only used by CBNZ, CBZ which is conditional based on 216// a register value even though the instruction is always unconditional. |
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215def template BranchImmRegConstructor {{ 216 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 217 int32_t _imm, 218 IntRegIndex _op1) 219 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 220 { 221 %(constructor)s; | 217def template BranchImmRegConstructor {{ 218 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 219 int32_t _imm, 220 IntRegIndex _op1) 221 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 222 { 223 %(constructor)s; |
222 if (!(condCode == COND_AL || condCode == COND_UC)) { 223 for (int x = 0; x < _numDestRegs; x++) { 224 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 225 } 226 flags[IsCondControl] = true; 227 } else { 228 flags[IsUncondControl] = true; 229 } | 224 flags[IsCondControl] = true; |
230 } 231}}; 232 233def template BranchTarget {{ 234 235 ArmISA::PCState 236 %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 237 { 238 %(op_decl)s; 239 %(op_rd)s; 240 241 ArmISA::PCState pcs = branchPC; 242 %(brTgtCode)s 243 pcs.advance(); 244 return pcs; 245 } 246}}; 247 248 | 225 } 226}}; 227 228def template BranchTarget {{ 229 230 ArmISA::PCState 231 %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 232 { 233 %(op_decl)s; 234 %(op_rd)s; 235 236 ArmISA::PCState pcs = branchPC; 237 %(brTgtCode)s 238 pcs.advance(); 239 return pcs; 240 } 241}}; 242 243 |