branch.isa (7848:cc5e64f8423f) | branch.isa (8146:18368caa8489) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 43 unchanged lines hidden (view full) --- 52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 43 unchanged lines hidden (view full) --- 52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } |
60 flags[IsCondControl] = true; 61 } else { 62 flags[IsUncondControl] = true; |
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60 } | 63 } |
64 |
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61 } 62}}; 63 64def template BranchImmCondDeclare {{ 65class %(class_name)s : public %(base_class)s 66{ 67 public: 68 // Constructor 69 %(class_name)s(ExtMachInst machInst, int32_t _imm, 70 ConditionCode _condCode); 71 %(BasicExecDeclare)s | 65 } 66}}; 67 68def template BranchImmCondDeclare {{ 69class %(class_name)s : public %(base_class)s 70{ 71 public: 72 // Constructor 73 %(class_name)s(ExtMachInst machInst, int32_t _imm, 74 ConditionCode _condCode); 75 %(BasicExecDeclare)s |
76 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; |
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72}; 73}}; 74 75def template BranchImmCondConstructor {{ 76 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 77 int32_t _imm, 78 ConditionCode _condCode) 79 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 80 _imm, _condCode) 81 { 82 %(constructor)s; 83 if (!(condCode == COND_AL || condCode == COND_UC)) { 84 for (int x = 0; x < _numDestRegs; x++) { 85 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 86 } | 77}; 78}}; 79 80def template BranchImmCondConstructor {{ 81 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 82 int32_t _imm, 83 ConditionCode _condCode) 84 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 85 _imm, _condCode) 86 { 87 %(constructor)s; 88 if (!(condCode == COND_AL || condCode == COND_UC)) { 89 for (int x = 0; x < _numDestRegs; x++) { 90 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 91 } |
92 flags[IsCondControl] = true; 93 } else { 94 flags[IsUncondControl] = true; |
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87 } 88 } 89}}; 90 91def template BranchRegDeclare {{ 92class %(class_name)s : public %(base_class)s 93{ 94 public: --- 8 unchanged lines hidden (view full) --- 103 IntRegIndex _op1) 104 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 105 { 106 %(constructor)s; 107 if (!(condCode == COND_AL || condCode == COND_UC)) { 108 for (int x = 0; x < _numDestRegs; x++) { 109 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 110 } | 95 } 96 } 97}}; 98 99def template BranchRegDeclare {{ 100class %(class_name)s : public %(base_class)s 101{ 102 public: --- 8 unchanged lines hidden (view full) --- 111 IntRegIndex _op1) 112 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 113 { 114 %(constructor)s; 115 if (!(condCode == COND_AL || condCode == COND_UC)) { 116 for (int x = 0; x < _numDestRegs; x++) { 117 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 118 } |
119 flags[IsCondControl] = true; 120 } else { 121 flags[IsUncondControl] = true; |
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111 } 112 } 113}}; 114 115def template BranchRegCondDeclare {{ 116class %(class_name)s : public %(base_class)s 117{ 118 public: --- 11 unchanged lines hidden (view full) --- 130 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 131 _op1, _condCode) 132 { 133 %(constructor)s; 134 if (!(condCode == COND_AL || condCode == COND_UC)) { 135 for (int x = 0; x < _numDestRegs; x++) { 136 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 137 } | 122 } 123 } 124}}; 125 126def template BranchRegCondDeclare {{ 127class %(class_name)s : public %(base_class)s 128{ 129 public: --- 11 unchanged lines hidden (view full) --- 141 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 142 _op1, _condCode) 143 { 144 %(constructor)s; 145 if (!(condCode == COND_AL || condCode == COND_UC)) { 146 for (int x = 0; x < _numDestRegs; x++) { 147 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 148 } |
149 flags[IsCondControl] = true; 150 } else { 151 flags[IsUncondControl] = true; |
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138 } 139 } 140}}; 141 142def template BranchRegRegDeclare {{ 143class %(class_name)s : public %(base_class)s 144{ 145 public: --- 25 unchanged lines hidden (view full) --- 171 IntRegIndex _op2) 172 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 173 { 174 %(constructor)s; 175 if (!(condCode == COND_AL || condCode == COND_UC)) { 176 for (int x = 0; x < _numDestRegs; x++) { 177 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 178 } | 152 } 153 } 154}}; 155 156def template BranchRegRegDeclare {{ 157class %(class_name)s : public %(base_class)s 158{ 159 public: --- 25 unchanged lines hidden (view full) --- 185 IntRegIndex _op2) 186 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 187 { 188 %(constructor)s; 189 if (!(condCode == COND_AL || condCode == COND_UC)) { 190 for (int x = 0; x < _numDestRegs; x++) { 191 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 192 } |
193 flags[IsCondControl] = true; 194 } else { 195 flags[IsUncondControl] = true; |
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179 } 180 } 181}}; 182 183def template BranchImmRegDeclare {{ 184class %(class_name)s : public %(base_class)s 185{ 186 public: --- 10 unchanged lines hidden (view full) --- 197 IntRegIndex _op1) 198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 199 { 200 %(constructor)s; 201 if (!(condCode == COND_AL || condCode == COND_UC)) { 202 for (int x = 0; x < _numDestRegs; x++) { 203 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 204 } | 196 } 197 } 198}}; 199 200def template BranchImmRegDeclare {{ 201class %(class_name)s : public %(base_class)s 202{ 203 public: --- 10 unchanged lines hidden (view full) --- 214 IntRegIndex _op1) 215 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 216 { 217 %(constructor)s; 218 if (!(condCode == COND_AL || condCode == COND_UC)) { 219 for (int x = 0; x < _numDestRegs; x++) { 220 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 221 } |
222 flags[IsCondControl] = true; 223 } else { 224 flags[IsUncondControl] = true; |
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205 } 206 } 207}}; | 225 } 226 } 227}}; |
228 229def template BranchTarget {{ 230 231 ArmISA::PCState 232 %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 233 { 234 %(op_decl)s; 235 %(op_rd)s; 236 237 ArmISA::PCState pcs = branchPC; 238 %(brTgtCode)s 239 pcs.advance(); 240 return pcs; 241 } 242}}; 243 244 |
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